1 // SPDX-License-Identifier: GPL-2.0+
2 /* * CAAM control-plane driver backend
3  * Controller-level driver, kernel property detection, initialization
5  * Copyright 2008-2012 Freescale Semiconductor, Inc.
6  * Copyright 2018-2019, 2023 NXP
45 	/* INIT RNG in non-test mode */  in build_instantiation_desc()
95  * run_descriptor_deco0 - runs a descriptor on DECO0, under direct control of
97  * @ctrldev - pointer to device
98  * @status - descriptor status, after being run
100  * Return: - 0 if no error occurred
101  *	   - -ENODEV if the DECO couldn't be acquired
102  *	   - -EAGAIN if an error occurred while executing the descriptor
108 	struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;  in run_descriptor_deco0()
109 	struct caam_deco __iomem *deco = ctrlpriv->deco;  in run_descriptor_deco0()
115 	if (ctrlpriv->virt_en == 1 ||  in run_descriptor_deco0()
121 		clrsetbits_32(&ctrl->deco_rsr, 0, DECORSR_JR0);  in run_descriptor_deco0()
123 		while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) &&  in run_descriptor_deco0()
124 		       --timeout)  in run_descriptor_deco0()
130 	clrsetbits_32(&ctrl->deco_rq, 0, DECORR_RQD0ENABLE);  in run_descriptor_deco0()
132 	while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) &&  in run_descriptor_deco0()
133 								 --timeout)  in run_descriptor_deco0()
138 		clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);  in run_descriptor_deco0()
139 		return -ENODEV;  in run_descriptor_deco0()
143 		wr_reg32(&deco->descbuf[i], caam32_to_cpu(*(desc + i)));  in run_descriptor_deco0()
154 	clrsetbits_32(&deco->jr_ctl_hi, 0, flags);  in run_descriptor_deco0()
158 		deco_dbg_reg = rd_reg32(&deco->desc_dbg);  in run_descriptor_deco0()
160 		if (ctrlpriv->era < 10)  in run_descriptor_deco0()
164 			deco_state = (rd_reg32(&deco->dbg_exec) &  in run_descriptor_deco0()
176 	} while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout);  in run_descriptor_deco0()
178 	*status = rd_reg32(&deco->op_status_hi) &  in run_descriptor_deco0()
181 	if (ctrlpriv->virt_en == 1)  in run_descriptor_deco0()
182 		clrsetbits_32(&ctrl->deco_rsr, DECORSR_JR0, 0);  in run_descriptor_deco0()
185 	clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);  in run_descriptor_deco0()
188 		return -EAGAIN;  in run_descriptor_deco0()
194  * deinstantiate_rng - builds and executes a descriptor on DECO0,
196  * @ctrldev - pointer to device
197  * @state_handle_mask - bitmask containing the instantiation status
201  * Return: - 0 if no error occurred
202  *	   - -ENOMEM if there isn't enough memory to allocate the descriptor
203  *	   - -ENODEV if DECO0 couldn't be acquired
204  *	   - -EAGAIN if an error occurred when executing the descriptor
213 		return -ENOMEM;  in deinstantiate_rng()
253 	 * De-initialize RNG state handles initialized by this driver.  in devm_deinstantiate_rng()
256 	if (ctrlpriv->rng4_sh_init)  in devm_deinstantiate_rng()
257 		deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init);  in devm_deinstantiate_rng()
261  * instantiate_rng - builds and executes a descriptor on DECO0,
263  * @ctrldev - pointer to device
264  * @state_handle_mask - bitmask containing the instantiation status
268  * @gen_sk  - generate data to be loaded into the JDKEK, TDKEK and TDSK;
272  * Return: - 0 if no error occurred
273  *	   - -ENOMEM if there isn't enough memory to allocate the descriptor
274  *	   - -ENODEV if DECO0 couldn't be acquired
275  *	   - -EAGAIN if an error occurred when executing the descriptor
287 	ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;  in instantiate_rng()
290 		return -ENOMEM;  in instantiate_rng()
335 		rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_MASK;  in instantiate_rng()
338 			ret = -EAGAIN;  in instantiate_rng()
354  * kick_trng - sets the various parameters for enabling the initialization
356  * @dev - pointer to the controller device
357  * @ent_delay - Defines the length (in system clocks) of each entropy sample.
366 	ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;  in kick_trng()
367 	r4tst = &ctrl->r4tst[0];  in kick_trng()
372 	 * force re-generation.  in kick_trng()
374 	clrsetbits_32(&r4tst->rtmctl, 0, RTMCTL_PRGM | RTMCTL_ACC);  in kick_trng()
377 	 * Performance-wise, it does not make sense to  in kick_trng()
382 	rtsdctl = rd_reg32(&r4tst->rtsdctl);  in kick_trng()
387 		wr_reg32(&r4tst->rtfrqmin, val >> 2);  in kick_trng()
389 		wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE);  in kick_trng()
392 	wr_reg32(&r4tst->rtsdctl, (val << RTSDCTL_ENT_DLY_SHIFT) |  in kick_trng()
396 	 * To avoid reprogramming the self-test parameters over and over again,  in kick_trng()
400 		wr_reg32(&r4tst->rtscmisc, (2 << 16) | 32);  in kick_trng()
401 		wr_reg32(&r4tst->rtpkrrng, 570);  in kick_trng()
402 		wr_reg32(&r4tst->rtpkrmax, 1600);  in kick_trng()
403 		wr_reg32(&r4tst->rtscml, (122 << 16) | 317);  in kick_trng()
404 		wr_reg32(&r4tst->rtscrl[0], (80 << 16) | 107);  in kick_trng()
405 		wr_reg32(&r4tst->rtscrl[1], (57 << 16) | 62);  in kick_trng()
406 		wr_reg32(&r4tst->rtscrl[2], (39 << 16) | 39);  in kick_trng()
407 		wr_reg32(&r4tst->rtscrl[3], (27 << 16) | 26);  in kick_trng()
408 		wr_reg32(&r4tst->rtscrl[4], (19 << 16) | 18);  in kick_trng()
409 		wr_reg32(&r4tst->rtscrl[5], (18 << 16) | 17);  in kick_trng()
416 	clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM | RTMCTL_ACC,  in kick_trng()
425 		u8 era;  in caam_get_era_from_hw()  member
442 	u8 maj_rev, era;  in caam_get_era_from_hw()  local
446 	ccbvid = rd_reg32(&perfmon->ccb_id);  in caam_get_era_from_hw()
447 	era = (ccbvid & CCBVID_ERA_MASK) >> CCBVID_ERA_SHIFT;  in caam_get_era_from_hw()
448 	if (era)	/* This is '0' prior to CAAM ERA-6 */  in caam_get_era_from_hw()
449 		return era;  in caam_get_era_from_hw()
451 	id_ms = rd_reg32(&perfmon->caam_id_ms);  in caam_get_era_from_hw()
457 			return id[i].era;  in caam_get_era_from_hw()
459 	return -ENOTSUPP;  in caam_get_era_from_hw()
463  * caam_get_era() - Return the ERA of the SEC on SoC, based
464  * on "sec-era" optional property in the DTS. This property is updated
465  * by u-boot.
467  * era via register reads will be made.
477 	caam_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");  in caam_get_era()
478 	ret = of_property_read_u32(caam_node, "fsl,sec-era", &prop);  in caam_get_era()
507 		.compatible = "fsl,sec-v4.0",
585 	clk_bulk_disable_unprepare(ctrlpriv->num_clks, ctrlpriv->clks);  in disable_clocks()
593 	ctrlpriv->num_clks = data->num_clks;  in init_clocks()
594 	ctrlpriv->clks = devm_kmemdup(dev, data->clks,  in init_clocks()
595 				      data->num_clks * sizeof(data->clks[0]),  in init_clocks()
597 	if (!ctrlpriv->clks)  in init_clocks()
598 		return -ENOMEM;  in init_clocks()
600 	ret = devm_clk_bulk_get(dev, ctrlpriv->num_clks, ctrlpriv->clks);  in init_clocks()
607 	ret = clk_bulk_prepare_enable(ctrlpriv->num_clks, ctrlpriv->clks);  in init_clocks()
626 	if (mc_version->major > major)  in check_version()
629 	if (mc_version->major == major) {  in check_version()
630 		if (mc_version->minor > minor)  in check_version()
633 		if (mc_version->minor == minor &&  in check_version()
634 		    mc_version->revision > revision)  in check_version()
652 	struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;  in caam_ctrl_rng_init()
656 	if (ctrlpriv->era < 10) {  in caam_ctrl_rng_init()
659 		perfmon = ctrlpriv->total_jobrs ?  in caam_ctrl_rng_init()
660 			  (struct caam_perfmon __iomem *)&ctrlpriv->jr[0]->perfmon :  in caam_ctrl_rng_init()
661 			  (struct caam_perfmon __iomem *)&ctrl->perfmon;  in caam_ctrl_rng_init()
663 		rng_vid = (rd_reg32(&perfmon->cha_id_ls) &  in caam_ctrl_rng_init()
668 		vreg = ctrlpriv->total_jobrs ?  in caam_ctrl_rng_init()
669 			(struct version_regs __iomem *)&ctrlpriv->jr[0]->vreg :  in caam_ctrl_rng_init()
670 			(struct version_regs __iomem *)&ctrl->vreg;  in caam_ctrl_rng_init()
672 		rng_vid = (rd_reg32(&vreg->rng) & CHA_VER_VID_MASK) >>  in caam_ctrl_rng_init()
677 	 * If SEC has RNG version >= 4 and RNG state handle has not been  in caam_ctrl_rng_init()
681 	if (!(ctrlpriv->mc_en && ctrlpriv->pr_support) && rng_vid >= 4) {  in caam_ctrl_rng_init()
682 		ctrlpriv->rng4_sh_init =  in caam_ctrl_rng_init()
683 			rd_reg32(&ctrl->r4tst[0].rdsta);  in caam_ctrl_rng_init()
690 		gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1;  in caam_ctrl_rng_init()
691 		ctrlpriv->rng4_sh_init &= RDSTA_MASK;  in caam_ctrl_rng_init()
694 				rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_MASK;  in caam_ctrl_rng_init()
697 			 * (e.g. u-boot) then it is assumed that the entropy  in caam_ctrl_rng_init()
705 			if (!(ctrlpriv->rng4_sh_init || inst_handles)) {  in caam_ctrl_rng_init()
730 			if (ret == -EAGAIN)  in caam_ctrl_rng_init()
736 		} while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX));  in caam_ctrl_rng_init()
745 		ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_MASK;  in caam_ctrl_rng_init()
748 		clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE);  in caam_ctrl_rng_init()
767 	struct caam_ctl_state *state = &ctrlpriv->state;  in caam_state_save()
768 	struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;  in caam_state_save()
772 	state->mcr = rd_reg32(&ctrl->mcr);  in caam_state_save()
773 	state->scfgr = rd_reg32(&ctrl->scfgr);  in caam_state_save()
775 	deco_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) &  in caam_state_save()
778 		state->deco_mid[i].liodn_ms =  in caam_state_save()
779 			rd_reg32(&ctrl->deco_mid[i].liodn_ms);  in caam_state_save()
780 		state->deco_mid[i].liodn_ls =  in caam_state_save()
781 			rd_reg32(&ctrl->deco_mid[i].liodn_ls);  in caam_state_save()
784 	jr_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) &  in caam_state_save()
787 		state->jr_mid[i].liodn_ms =  in caam_state_save()
788 			rd_reg32(&ctrl->jr_mid[i].liodn_ms);  in caam_state_save()
789 		state->jr_mid[i].liodn_ls =  in caam_state_save()
790 			rd_reg32(&ctrl->jr_mid[i].liodn_ls);  in caam_state_save()
797 	const struct caam_ctl_state *state = &ctrlpriv->state;  in caam_state_restore()
798 	struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;  in caam_state_restore()
802 	wr_reg32(&ctrl->mcr, state->mcr);  in caam_state_restore()
803 	wr_reg32(&ctrl->scfgr, state->scfgr);  in caam_state_restore()
805 	deco_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) &  in caam_state_restore()
808 		wr_reg32(&ctrl->deco_mid[i].liodn_ms,  in caam_state_restore()
809 			 state->deco_mid[i].liodn_ms);  in caam_state_restore()
810 		wr_reg32(&ctrl->deco_mid[i].liodn_ls,  in caam_state_restore()
811 			 state->deco_mid[i].liodn_ls);  in caam_state_restore()
814 	jr_inst = (rd_reg32(&ctrl->perfmon.cha_num_ms) &  in caam_state_restore()
817 		wr_reg32(&ctrl->jr_mid[i].liodn_ms,  in caam_state_restore()
818 			 state->jr_mid[i].liodn_ms);  in caam_state_restore()
819 		wr_reg32(&ctrl->jr_mid[i].liodn_ls,  in caam_state_restore()
820 			 state->jr_mid[i].liodn_ls);  in caam_state_restore()
823 	if (ctrlpriv->virt_en == 1)  in caam_state_restore()
824 		clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START |  in caam_state_restore()
833 	if (ctrlpriv->caam_off_during_pm && !ctrlpriv->optee_en)  in caam_ctrl_suspend()
844 	if (ctrlpriv->caam_off_during_pm && !ctrlpriv->optee_en) {  in caam_ctrl_resume()
875 	ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(*ctrlpriv), GFP_KERNEL);  in caam_probe()
877 		return -ENOMEM;  in caam_probe()
879 	dev = &pdev->dev;  in caam_probe()
881 	nprop = pdev->dev.of_node;  in caam_probe()
885 		return -EPROBE_DEFER;  in caam_probe()
889 	ctrlpriv->caam_off_during_pm = caam_imx && caam_off_during_pm();  in caam_probe()
893 		 * Until Layerscape and i.MX OP-TEE get in sync,  in caam_probe()
894 		 * only i.MX OP-TEE use cases disallow access to  in caam_probe()
897 		np = of_find_compatible_node(NULL, NULL, "linaro,optee-tz");  in caam_probe()
898 		ctrlpriv->optee_en = !!np;  in caam_probe()
901 		reg_access = !ctrlpriv->optee_en;  in caam_probe()
903 		if (!imx_soc_match->data) {  in caam_probe()
905 			return -EINVAL;  in caam_probe()
908 		imx_soc_data = imx_soc_match->data;  in caam_probe()
909 		reg_access = reg_access && imx_soc_data->page0_access;  in caam_probe()
913 		if (!imx_soc_data->num_clks)  in caam_probe()
916 		ret = init_clocks(dev, imx_soc_match->data);  in caam_probe()
933 		if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") ||  in caam_probe()
934 		    of_device_is_compatible(np, "fsl,sec4.0-job-ring")) {  in caam_probe()
939 					np->full_name);  in caam_probe()
943 			ctrlpriv->jr[ring] = (struct caam_job_ring __iomem __force *)  in caam_probe()
946 			ctrlpriv->total_jobrs++;  in caam_probe()
955 	perfmon = ring ? (struct caam_perfmon __iomem *)&ctrlpriv->jr[0]->perfmon :  in caam_probe()
956 			 (struct caam_perfmon __iomem *)&ctrl->perfmon;  in caam_probe()
958 	caam_little_end = !(bool)(rd_reg32(&perfmon->status) &  in caam_probe()
960 	comp_params = rd_reg32(&perfmon->comp_parms_ms);  in caam_probe()
962 	    rd_reg32(&ctrl->mcr) & MCFGR_LONG_PTR)  in caam_probe()
967 	ctrlpriv->qi_present = !!(comp_params & CTPR_MS_QI_MASK);  in caam_probe()
971 	if (ctrlpriv->qi_present && !caam_dpaa2) {  in caam_probe()
974 			return -EPROBE_DEFER;  in caam_probe()
977 			return -ENODEV;  in caam_probe()
982 			return -EPROBE_DEFER;  in caam_probe()
985 			return -ENODEV;  in caam_probe()
999 	ctrlpriv->ctrl = (struct caam_ctrl __iomem __force *)ctrl;  in caam_probe()
1000 	ctrlpriv->assure = (struct caam_assurance __iomem __force *)  in caam_probe()
1004 	ctrlpriv->deco = (struct caam_deco __iomem __force *)  in caam_probe()
1010 	ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0);  in caam_probe()
1011 	np = of_find_compatible_node(NULL, NULL, "fsl,qoriq-mc");  in caam_probe()
1012 	ctrlpriv->mc_en = !!np;  in caam_probe()
1016 	if (ctrlpriv->mc_en) {  in caam_probe()
1021 			ctrlpriv->pr_support = check_version(mc_version, 10, 20,  in caam_probe()
1024 			return -EPROBE_DEFER;  in caam_probe()
1037 	if (!ctrlpriv->mc_en)  in caam_probe()
1038 		clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK,  in caam_probe()
1042 	handle_imx6_err005766(&ctrl->mcr);  in caam_probe()
1048 	scfgr = rd_reg32(&ctrl->scfgr);  in caam_probe()
1050 	ctrlpriv->virt_en = 0;  in caam_probe()
1058 				ctrlpriv->virt_en = 1;  in caam_probe()
1062 				ctrlpriv->virt_en = 1;  in caam_probe()
1065 	if (ctrlpriv->virt_en == 1)  in caam_probe()
1066 		clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START |  in caam_probe()
1077 	ctrlpriv->era = caam_get_era(perfmon);  in caam_probe()
1078 	ctrlpriv->domain = iommu_get_domain_for_dev(dev);  in caam_probe()
1091 	if (ctrlpriv->qi_present && !caam_dpaa2) {  in caam_probe()
1092 		ctrlpriv->qi = (struct caam_queue_if __iomem __force *)  in caam_probe()
1097 		wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN);  in caam_probe()
1099 		/* If QMAN driver is present, init CAAM-QI backend */  in caam_probe()
1108 	if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) {  in caam_probe()
1110 		return -ENOMEM;  in caam_probe()
1113 	comp_params = rd_reg32(&perfmon->comp_parms_ls);  in caam_probe()
1114 	ctrlpriv->blob_present = !!(comp_params & CTPR_LS_BLOB);  in caam_probe()
1117 	 * Some SoCs like the LS1028A (non-E) indicate CTPR_LS_BLOB support,  in caam_probe()
1121 	if (ctrlpriv->era < 10) {  in caam_probe()
1122 		ctrlpriv->blob_present = ctrlpriv->blob_present &&  in caam_probe()
1123 			(rd_reg32(&perfmon->cha_num_ls) & CHA_ID_LS_AES_MASK);  in caam_probe()
1127 		vreg =  ctrlpriv->total_jobrs ?  in caam_probe()
1128 			(struct version_regs __iomem *)&ctrlpriv->jr[0]->vreg :  in caam_probe()
1129 			(struct version_regs __iomem *)&ctrl->vreg;  in caam_probe()
1131 		ctrlpriv->blob_present = ctrlpriv->blob_present &&  in caam_probe()
1132 			(rd_reg32(&vreg->aesa) & CHA_VER_MISC_AES_NUM_MASK);  in caam_probe()
1141 	caam_id = (u64)rd_reg32(&perfmon->caam_id_ms) << 32 |  in caam_probe()
1142 		  (u64)rd_reg32(&perfmon->caam_id_ls);  in caam_probe()
1145 	dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,  in caam_probe()
1146 		 ctrlpriv->era);  in caam_probe()
1148 		 ctrlpriv->total_jobrs, ctrlpriv->qi_present);  in caam_probe()
1170 MODULE_AUTHOR("Freescale Semiconductor - NMG/STC");