33  * ACRY register definitions *
36 #define ASPEED_ACRY_TRIGGER		0x000	/* ACRY Engine Control: trigger */
37 #define ASPEED_ACRY_DMA_CMD		0x048	/* ACRY Engine Control: Command */
38 #define ASPEED_ACRY_DMA_SRC_BASE	0x04C	/* ACRY DRAM base address for DMA */
39 #define ASPEED_ACRY_DMA_LEN		0x050	/* ACRY Data Length of DMA */
40 #define ASPEED_ACRY_RSA_KEY_LEN		0x058	/* ACRY RSA Exp/Mod Key Length (Bits) */
41 #define ASPEED_ACRY_INT_MASK		0x3F8	/* ACRY Interrupt Mask */
42 #define ASPEED_ACRY_STATUS		0x3FC	/* ACRY Interrupt Status */
57 /* acry isr */
61 #define ASPEED_ACRY_SRAM_MAX_LEN	2048	/* ACRY SRAM maximum length (Bytes) */
62 #define ASPEED_ACRY_RSA_MAX_KEY_LEN	512	/* ACRY RSA maximum key length (Bytes) */
75 #define ast_acry_write(acry, val, offset)	\  argument
76 	writel((val), (acry)->regs + (offset))
78 #define ast_acry_read(acry, offset)		\  argument
79 	readl((acry)->regs + (offset))
97 	/* ACRY output SRAM buffer */
100 	/* ACRY input DMA buffer */
106 	/* ACRY SRAM memory mapped */
244  * - ACRY SRAM memory layout should reverse the order of source data:
313 	/* Disable ACRY SRAM protection */  in aspeed_acry_rsa_transfer()
398 	/* Enable ACRY SRAM protection */  in aspeed_acry_rsa_trigger()
651 /* ACRY interrupt service routine. */
676  * ACRY SRAM has its own memory layout.
703 	{ .compatible = "aspeed,ast2600-acry", },
744 		dev_err(dev, "Failed to get acry clk\n");  in aspeed_acry_probe()
772 	/* Initialize ACRY SRAM index */  in aspeed_acry_probe()
785 	dev_info(dev, "Aspeed ACRY Accelerator successfully registered\n");  in aspeed_acry_probe()
821 MODULE_DESCRIPTION("ASPEED ACRY driver for hardware RSA Engine");