Lines Matching +full:hardware +full:- +full:protected
1 # SPDX-License-Identifier: GPL-2.0-only
4 bool "Hardware crypto devices"
7 Say Y here to get to see options for hardware crypto devices and
39 called padlock-aes.
53 called padlock-sha.
61 Say 'Y' here to use the AMD Geode LX processor on-board AES
65 will be called geode-aes.
79 tristate "Kernel API for protected key handling"
83 for creation and handling of protected keys. Other parts of the
86 The protected key support is distributed into:
87 - A pkey base and API kernel module (pkey.ko) which offers the
89 and the sysfs API and the in-kernel API to the crypto cipher
90 implementations using protected key.
91 - A pkey pckmo kernel module (pkey-pckmo.ko) which is automatically
92 loaded when pckmo support (that is generation of protected keys
94 - A pkey CCA kernel module (pkey-cca.ko) which is automatically
96 - A pkey EP11 kernel module (pkey-ep11.ko) which is automatically
100 API for protected key handling.
107 This is the CCA support handler for deriving protected keys
109 way to make protected keys from clear key values.
115 this option unless you are sure you never need to derive protected
123 This is the EP11 support handler for deriving protected keys
125 way to make protected keys from clear key values.
131 this option unless you are sure you never need to derive protected
138 This is the PCKMO support handler for deriving protected keys
146 The PCKMO way of deriving protected keys from clear key material
147 is especially used during self test of protected key ciphers like
149 generate protected keys from clear key values.
152 this option unless you are sure you never need to derive protected
163 This is the s390 hardware accelerated implementation of the
164 AES cipher algorithms for use with protected key.
167 for example to use protected key encrypted devices.
176 and uses triple-DES to generate secure random numbers like the
177 ANSI X9.17 standard. User-space programs access the
178 pseudo-random-number device through the char device /dev/prandom.
194 sub-units. One set provides the Modular Arithmetic Unit,
295 This option provides the kernel-side support for the TRNG hardware
365 This driver provides kernel-side support through the
366 cryptographic API for the pseudo random number generator hardware
370 module will be called exynos-rng.
395 needed for small and zero-size messages.
403 This enables support for the NX hardware cryptographic accelerator
436 will be called atmel-aes.
449 will be called atmel-tdes.
462 will be called atmel-sha.
480 will be called atmel-ecc.
495 will be called atmel-sha204a.
519 co-processor on the die.
522 will be called mxs-dcp.
542 hardware. To compile this driver as a module, choose M here. The
574 (default), hashes-only, or skciphers-only.
577 multiple crypto requests. While the ipq40xx chips have 4-core CPUs, the
581 algorithms, sharing the load with the CPU. Enabling skciphers-only
591 - AES (CBC, CTR, ECB, XTS)
592 - 3DES (CBC, ECB)
593 - DES (CBC, ECB)
594 - SHA1, HMAC-SHA1
595 - SHA256, HMAC-SHA256
598 bool "Symmetric-key ciphers only"
601 Enable symmetric-key ciphers only:
602 - AES (CBC, CTR, ECB, XTS)
603 - 3DES (ECB, CBC)
604 - DES (ECB, CBC)
611 - SHA1, HMAC-SHA1
612 - SHA256, HMAC-SHA256
619 - authenc()
620 - ccm(aes)
621 - rfc4309(ccm(aes))
633 Small blocks are processed faster in software than hardware.
634 Considering the 256-bit ciphers, software is 2-3 times faster than
635 qce at 256-bytes, 30% faster at 512, and about even at 768-bytes.
636 With 128-bit keys, the break-even point would be around 1024-bytes.
639 cost in CPU usage. The minimum recommended setting is 16-bytes
640 (1 AES block), since AES-GCM will fail if you set it lower.
641 Setting this to zero will send all requests to the hardware.
643 Note that 192-bit keys are not supported by the hardware and are
645 are done by the hardware.
654 Generator hardware found on Qualcomm SoCs.
657 module will be called qcom-rng. If unsure, say N.
668 tristate "Imagination Technologies hardware hash accelerator"
676 hardware hash accelerator. Supporting MD5/SHA1/SHA224/SHA256
696 This driver interfaces with the hardware crypto accelerator.
724 Xilinx ZynqMP has AES-GCM engine used for symmetric key
730 tristate "Support for Xilinx ZynqMP SHA3 hardware accelerator"
735 This driver interfaces with SHA3 hardware engine.
777 This driver interfaces with the SafeXcel EIP-97 and EIP-197 cryptographic
781 Additionally, it accelerates combined AES-CBC/HMAC-SHA AEAD operations.
784 tristate "Support for Axis ARTPEC-6/7 hardware crypto acceleration."
797 Enables the driver for the on-chip crypto accelerator
827 Choose this if you wish to use hardware acceleration of
849 used for crypto offload. Select this if you want to use hardware