29 #define S5P_APLL_LOCK		S5P_CLKREG(0x00)
30 #define S5P_APLL_CON		S5P_CLKREG(0x100)
31 #define S5P_CLK_SRC0		S5P_CLKREG(0x200)
32 #define S5P_CLK_SRC2		S5P_CLKREG(0x208)
33 #define S5P_CLK_DIV0		S5P_CLKREG(0x300)
34 #define S5P_CLK_DIV2		S5P_CLKREG(0x308)
35 #define S5P_CLK_DIV6		S5P_CLKREG(0x318)
36 #define S5P_CLKDIV_STAT0	S5P_CLKREG(0x1000)
37 #define S5P_CLKDIV_STAT1	S5P_CLKREG(0x1004)
38 #define S5P_CLKMUX_STAT0	S5P_CLKREG(0x1100)
39 #define S5P_CLKMUX_STAT1	S5P_CLKREG(0x1104)
41 #define S5P_ARM_MCS_CON		S5P_CLKREG(0x6100)
45 #define S5P_CLKSRC0_MUX200_MASK		(0x1 << S5P_CLKSRC0_MUX200_SHIFT)
46 #define S5P_CLKSRC0_MUX166_MASK		(0x1<<20)
47 #define S5P_CLKSRC0_MUX133_MASK		(0x1<<24)
50 #define S5P_CLKSRC2_G3D_SHIFT           (0)
51 #define S5P_CLKSRC2_G3D_MASK            (0x3 << S5P_CLKSRC2_G3D_SHIFT)
53 #define S5P_CLKSRC2_MFC_MASK            (0x3 << S5P_CLKSRC2_MFC_SHIFT)
56 #define S5P_CLKDIV0_APLL_SHIFT		(0)
57 #define S5P_CLKDIV0_APLL_MASK		(0x7 << S5P_CLKDIV0_APLL_SHIFT)
59 #define S5P_CLKDIV0_A2M_MASK		(0x7 << S5P_CLKDIV0_A2M_SHIFT)
61 #define S5P_CLKDIV0_HCLK200_MASK	(0x7 << S5P_CLKDIV0_HCLK200_SHIFT)
63 #define S5P_CLKDIV0_PCLK100_MASK	(0x7 << S5P_CLKDIV0_PCLK100_SHIFT)
65 #define S5P_CLKDIV0_HCLK166_MASK	(0xF << S5P_CLKDIV0_HCLK166_SHIFT)
67 #define S5P_CLKDIV0_PCLK83_MASK		(0x7 << S5P_CLKDIV0_PCLK83_SHIFT)
69 #define S5P_CLKDIV0_HCLK133_MASK	(0xF << S5P_CLKDIV0_HCLK133_SHIFT)
71 #define S5P_CLKDIV0_PCLK66_MASK		(0x7 << S5P_CLKDIV0_PCLK66_SHIFT)
74 #define S5P_CLKDIV2_G3D_SHIFT           (0)
75 #define S5P_CLKDIV2_G3D_MASK            (0xF << S5P_CLKDIV2_G3D_SHIFT)
77 #define S5P_CLKDIV2_MFC_MASK            (0xF << S5P_CLKDIV2_MFC_SHIFT)
81 #define S5P_CLKDIV6_ONEDRAM_MASK        (0xF << S5P_CLKDIV6_ONEDRAM_SHIFT)
114 	LPDDR	= 0x1,
115 	LPDDR2	= 0x2,
116 	DDR2	= 0x4,
120 	DMC0 = 0,
125 	{0, L0, 1000*1000},
126 	{0, L1, 800*1000},
127 	{0, L2, 400*1000},
128 	{0, L3, 200*1000},
129 	{0, L4, 100*1000},
130 	{0, 0, CPUFREQ_TABLE_END},
176 	{0, 4, 4, 1, 3, 1, 4, 1, 3, 0, 0},
179 	{0, 3, 3, 1, 3, 1, 4, 1, 3, 0, 0},
182 	{1, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
185 	{3, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
188 	{7, 7, 0, 0, 7, 0, 9, 0, 7, 0, 0},
194  * ch: DMC port number 0 or 1
203 		reg = (dmc_base[0] + 0x30);  in s5pv210_set_refresh()
205 		reg = (dmc_base[1] + 0x30);  in s5pv210_set_refresh()
227 	unsigned int pll_changing = 0;  in s5pv210_target()
228 	unsigned int bus_speed_changing = 0;  in s5pv210_target()
231 	int ret = 0;  in s5pv210_target()
275 		 * expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287  in s5pv210_target()
324 		 * code. 0x287@83Mhz  in s5pv210_target()
332 		reg |= (0x1 << S5P_CLKSRC0_MUX200_SHIFT);  in s5pv210_target()
337 		} while (reg & (0x1 << 18));  in s5pv210_target()
349 	reg |= ((clkdiv_val[index][0] << S5P_CLKDIV0_APLL_SHIFT) |  in s5pv210_target()
362 	} while (reg & 0xff);  in s5pv210_target()
366 	reg &= ~0x3;  in s5pv210_target()
368 		reg |= 0x3;  in s5pv210_target()
370 		reg |= 0x1;  in s5pv210_target()
375 		/* 5. Set Lock time = 30us*24Mhz = 0x2cf */  in s5pv210_target()
376 		writel_relaxed(0x2cf, S5P_APLL_LOCK);  in s5pv210_target()
390 		} while (!(reg & (0x1 << 29)));  in s5pv210_target()
399 		reg |= (0 << S5P_CLKSRC2_G3D_SHIFT) |  in s5pv210_target()
400 			(0 << S5P_CLKSRC2_MFC_SHIFT);  in s5pv210_target()
425 		reg |= (0x0 << S5P_CLKSRC0_MUX200_SHIFT);  in s5pv210_target()
430 		} while (reg & (0x1 << 18));  in s5pv210_target()
434 		 * L4 : DMC1 = 100Mhz 7.8us/(1/100) = 0x30c  in s5pv210_target()
435 		 * Others : DMC1 = 200Mhz 7.8us/(1/200) = 0x618  in s5pv210_target()
492 	val = readl_relaxed(dmc_reg + 0x4);  in check_mem_type()
493 	val = (val & (0xf << 8));  in check_mem_type()
519 	if (policy->cpu != 0) {  in s5pv210_cpu_init()
528 	mem_type = check_mem_type(dmc_base[0]);  in s5pv210_cpu_init()
537 	s5pv210_dram_conf[0].refresh = (readl_relaxed(dmc_base[0] + 0x30) * 1000);  in s5pv210_cpu_init()
538 	s5pv210_dram_conf[0].freq = clk_get_rate(dmc0_clk);  in s5pv210_cpu_init()
540 	s5pv210_dram_conf[1].refresh = (readl_relaxed(dmc_base[1] + 0x30) * 1000);  in s5pv210_cpu_init()
545 	return 0;  in s5pv210_cpu_init()
560 	policy = cpufreq_cpu_get(0);  in s5pv210_cpufreq_reboot_notifier_event()
566 	ret = cpufreq_driver_target(policy, SLEEP_FREQ, 0);  in s5pv210_cpufreq_reboot_notifier_event()
569 	if (ret < 0)  in s5pv210_cpufreq_reboot_notifier_event()
595 	int id, result = 0;  in s5pv210_cpufreq_probe()
624 	clk_base = of_iomap(np, 0);  in s5pv210_cpufreq_probe()
634 		if (id < 0 || id >= ARRAY_SIZE(dmc_base)) {  in s5pv210_cpufreq_probe()
641 		dmc_base[id] = of_iomap(np, 0);  in s5pv210_cpufreq_probe()
650 	for (id = 0; id < ARRAY_SIZE(dmc_base); ++id) {  in s5pv210_cpufreq_probe()
663 	for (id = 0; id < ARRAY_SIZE(dmc_base); ++id)  in s5pv210_cpufreq_probe()