Lines Matching +full:activity +full:- +full:signal +full:- +full:sources
1 // SPDX-License-Identifier: GPL-2.0+
3 * Hardware driver for DAQ-STC based boards
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1997-2001 David A. Schleef <ds@schleef.org>
7 * Copyright (C) 2002-2006 Frank Mori Hess <fmhess@users.sourceforge.net>
17 * 340747b.pdf AT-MIO E series Register Level Programmer Manual
19 * 340934b.pdf DAQ-STC reference manual
29 * 320906c.pdf maximum signal ratings
31 * 321791a.pdf discontinuation of at-mio-16e-10 rev. c
32 * 321808a.pdf about at-mio-16e-10 rev P
33 * 321837a.pdf discontinuation of at-mio-16de-10 rev d
34 * 321838a.pdf about at-mio-16de-10 rev N
37 * - the interrupt routine needs to be cleaned up
39 * 2006-02-07: S-Series PCI-6143: Support has been added but is not
223 writel(data, dev->mmio + reg); in ni_writel()
228 writew(data, dev->mmio + reg); in ni_writew()
233 writeb(data, dev->mmio + reg); in ni_writeb()
238 return readl(dev->mmio + reg); in ni_readl()
243 return readw(dev->mmio + reg); in ni_readw()
248 return readb(dev->mmio + reg); in ni_readb()
255 outl(data, dev->iobase + reg); in ni_writel()
260 outw(data, dev->iobase + reg); in ni_writew()
265 outb(data, dev->iobase + reg); in ni_writeb()
270 return inl(dev->iobase + reg); in ni_readl()
275 return inw(dev->iobase + reg); in ni_readw()
280 return inb(dev->iobase + reg); in ni_readb()
289 * The AT-MIO and DAQCard devices map the low 8 STC registers to
293 * 611x devices map the read registers to iobase+(addr-1)*2.
294 * For now non-windowed STC access is disabled if a PCIMIO device
295 * is detected (devpriv->mite has been initialized).
362 [NISTC_INTA2_ENA_REG] = { 0, 0 }, /* E-Series only */
364 [NISTC_INTB2_ENA_REG] = { 0, 0 }, /* E-Series only */
386 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n", in m_series_stc_write()
391 switch (regmap->size) { in m_series_stc_write()
393 ni_writel(dev, data, regmap->mio_reg); in m_series_stc_write()
396 ni_writew(dev, data, regmap->mio_reg); in m_series_stc_write()
399 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n", in m_series_stc_write()
434 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n", in m_series_stc_read()
439 switch (regmap->size) { in m_series_stc_read()
441 return ni_readl(dev, regmap->mio_reg); in m_series_stc_read()
443 return ni_readw(dev, regmap->mio_reg); in m_series_stc_read()
445 return ni_readb(dev, regmap->mio_reg); in m_series_stc_read()
447 dev_warn(dev->class_dev, "%s: unmapped register=0x%x\n", in m_series_stc_read()
456 struct ni_private *devpriv = dev->private; in ni_stc_writew()
459 if (devpriv->is_m_series) { in ni_stc_writew()
462 spin_lock_irqsave(&devpriv->window_lock, flags); in ni_stc_writew()
463 if (!devpriv->mite && reg < 8) { in ni_stc_writew()
469 spin_unlock_irqrestore(&devpriv->window_lock, flags); in ni_stc_writew()
476 struct ni_private *devpriv = dev->private; in ni_stc_writel()
478 if (devpriv->is_m_series) { in ni_stc_writel()
488 struct ni_private *devpriv = dev->private; in ni_stc_readw()
492 if (devpriv->is_m_series) { in ni_stc_readw()
495 spin_lock_irqsave(&devpriv->window_lock, flags); in ni_stc_readw()
496 if (!devpriv->mite && reg < 8) { in ni_stc_readw()
502 spin_unlock_irqrestore(&devpriv->window_lock, flags); in ni_stc_readw()
509 struct ni_private *devpriv = dev->private; in ni_stc_readl()
512 if (devpriv->is_m_series) { in ni_stc_readl()
525 struct ni_private *devpriv = dev->private; in ni_set_bitfield()
528 spin_lock_irqsave(&devpriv->soft_reg_copy_lock, flags); in ni_set_bitfield()
531 devpriv->int_a_enable_reg &= ~bit_mask; in ni_set_bitfield()
532 devpriv->int_a_enable_reg |= bit_values & bit_mask; in ni_set_bitfield()
533 ni_stc_writew(dev, devpriv->int_a_enable_reg, reg); in ni_set_bitfield()
536 devpriv->int_b_enable_reg &= ~bit_mask; in ni_set_bitfield()
537 devpriv->int_b_enable_reg |= bit_values & bit_mask; in ni_set_bitfield()
538 ni_stc_writew(dev, devpriv->int_b_enable_reg, reg); in ni_set_bitfield()
541 devpriv->io_bidirection_pin_reg &= ~bit_mask; in ni_set_bitfield()
542 devpriv->io_bidirection_pin_reg |= bit_values & bit_mask; in ni_set_bitfield()
543 ni_stc_writew(dev, devpriv->io_bidirection_pin_reg, reg); in ni_set_bitfield()
546 devpriv->ai_ao_select_reg &= ~bit_mask; in ni_set_bitfield()
547 devpriv->ai_ao_select_reg |= bit_values & bit_mask; in ni_set_bitfield()
548 ni_writeb(dev, devpriv->ai_ao_select_reg, reg); in ni_set_bitfield()
551 devpriv->g0_g1_select_reg &= ~bit_mask; in ni_set_bitfield()
552 devpriv->g0_g1_select_reg |= bit_values & bit_mask; in ni_set_bitfield()
553 ni_writeb(dev, devpriv->g0_g1_select_reg, reg); in ni_set_bitfield()
556 devpriv->cdio_dma_select_reg &= ~bit_mask; in ni_set_bitfield()
557 devpriv->cdio_dma_select_reg |= bit_values & bit_mask; in ni_set_bitfield()
558 ni_writeb(dev, devpriv->cdio_dma_select_reg, reg); in ni_set_bitfield()
561 dev_err(dev->class_dev, "called with invalid register %d\n", in ni_set_bitfield()
565 spin_unlock_irqrestore(&devpriv->soft_reg_copy_lock, flags); in ni_set_bitfield()
578 struct ni_private *devpriv = dev->private; in ni_request_ai_mite_channel()
583 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in ni_request_ai_mite_channel()
584 mite_chan = mite_request_channel(devpriv->mite, devpriv->ai_mite_ring); in ni_request_ai_mite_channel()
586 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_request_ai_mite_channel()
587 dev_err(dev->class_dev, in ni_request_ai_mite_channel()
589 return -EBUSY; in ni_request_ai_mite_channel()
591 mite_chan->dir = COMEDI_INPUT; in ni_request_ai_mite_channel()
592 devpriv->ai_mite_chan = mite_chan; in ni_request_ai_mite_channel()
594 bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel); in ni_request_ai_mite_channel()
598 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_request_ai_mite_channel()
604 struct ni_private *devpriv = dev->private; in ni_request_ao_mite_channel()
609 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in ni_request_ao_mite_channel()
610 mite_chan = mite_request_channel(devpriv->mite, devpriv->ao_mite_ring); in ni_request_ao_mite_channel()
612 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_request_ao_mite_channel()
613 dev_err(dev->class_dev, in ni_request_ao_mite_channel()
615 return -EBUSY; in ni_request_ao_mite_channel()
617 mite_chan->dir = COMEDI_OUTPUT; in ni_request_ao_mite_channel()
618 devpriv->ao_mite_chan = mite_chan; in ni_request_ao_mite_channel()
620 bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel); in ni_request_ao_mite_channel()
624 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_request_ao_mite_channel()
632 struct ni_private *devpriv = dev->private; in ni_request_gpct_mite_channel()
633 struct ni_gpct *counter = &devpriv->counter_dev->counters[gpct_index]; in ni_request_gpct_mite_channel()
638 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in ni_request_gpct_mite_channel()
639 mite_chan = mite_request_channel(devpriv->mite, in ni_request_gpct_mite_channel()
640 devpriv->gpct_mite_ring[gpct_index]); in ni_request_gpct_mite_channel()
642 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_request_gpct_mite_channel()
643 dev_err(dev->class_dev, in ni_request_gpct_mite_channel()
645 return -EBUSY; in ni_request_gpct_mite_channel()
647 mite_chan->dir = direction; in ni_request_gpct_mite_channel()
650 bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel); in ni_request_gpct_mite_channel()
655 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_request_gpct_mite_channel()
661 struct ni_private *devpriv = dev->private; in ni_request_cdo_mite_channel()
666 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in ni_request_cdo_mite_channel()
667 mite_chan = mite_request_channel(devpriv->mite, devpriv->cdo_mite_ring); in ni_request_cdo_mite_channel()
669 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_request_cdo_mite_channel()
670 dev_err(dev->class_dev, in ni_request_cdo_mite_channel()
672 return -EBUSY; in ni_request_cdo_mite_channel()
674 mite_chan->dir = COMEDI_OUTPUT; in ni_request_cdo_mite_channel()
675 devpriv->cdo_mite_chan = mite_chan; in ni_request_cdo_mite_channel()
683 bits = NI_STC_DMA_CHAN_SEL(mite_chan->channel); in ni_request_cdo_mite_channel()
688 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_request_cdo_mite_channel()
696 struct ni_private *devpriv = dev->private; in ni_release_ai_mite_channel()
699 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in ni_release_ai_mite_channel()
700 if (devpriv->ai_mite_chan) { in ni_release_ai_mite_channel()
703 mite_release_channel(devpriv->ai_mite_chan); in ni_release_ai_mite_channel()
704 devpriv->ai_mite_chan = NULL; in ni_release_ai_mite_channel()
706 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_release_ai_mite_channel()
713 struct ni_private *devpriv = dev->private; in ni_release_ao_mite_channel()
716 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in ni_release_ao_mite_channel()
717 if (devpriv->ao_mite_chan) { in ni_release_ao_mite_channel()
720 mite_release_channel(devpriv->ao_mite_chan); in ni_release_ao_mite_channel()
721 devpriv->ao_mite_chan = NULL; in ni_release_ao_mite_channel()
723 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_release_ao_mite_channel()
731 struct ni_private *devpriv = dev->private; in ni_release_gpct_mite_channel()
734 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in ni_release_gpct_mite_channel()
735 if (devpriv->counter_dev->counters[gpct_index].mite_chan) { in ni_release_gpct_mite_channel()
737 devpriv->counter_dev->counters[gpct_index].mite_chan; in ni_release_gpct_mite_channel()
741 ni_tio_set_mite_channel(&devpriv->counter_dev->counters[gpct_index], in ni_release_gpct_mite_channel()
745 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_release_gpct_mite_channel()
750 struct ni_private *devpriv = dev->private; in ni_release_cdo_mite_channel()
753 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in ni_release_cdo_mite_channel()
754 if (devpriv->cdo_mite_chan) { in ni_release_cdo_mite_channel()
757 mite_release_channel(devpriv->cdo_mite_chan); in ni_release_cdo_mite_channel()
758 devpriv->cdo_mite_chan = NULL; in ni_release_cdo_mite_channel()
760 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_release_cdo_mite_channel()
766 struct ni_private *devpriv = dev->private; in ni_e_series_enable_second_irq()
770 if (devpriv->is_m_series || gpct_index > 1) in ni_e_series_enable_second_irq()
774 * e-series boards use the second irq signals to generate in ni_e_series_enable_second_irq()
792 struct ni_private *devpriv = dev->private; in ni_clear_ai_fifo()
796 if (devpriv->is_6143) { in ni_clear_ai_fifo()
807 dev_err(dev->class_dev, "FIFO flush timeout\n"); in ni_clear_ai_fifo()
810 if (devpriv->is_625x) { in ni_clear_ai_fifo()
832 struct ni_private *devpriv = dev->private; in ni_ao_win_outw()
835 spin_lock_irqsave(&devpriv->window_lock, flags); in ni_ao_win_outw()
838 spin_unlock_irqrestore(&devpriv->window_lock, flags); in ni_ao_win_outw()
844 struct ni_private *devpriv = dev->private; in ni_ao_win_outl()
847 spin_lock_irqsave(&devpriv->window_lock, flags); in ni_ao_win_outl()
850 spin_unlock_irqrestore(&devpriv->window_lock, flags); in ni_ao_win_outl()
855 struct ni_private *devpriv = dev->private; in ni_ao_win_inw()
859 spin_lock_irqsave(&devpriv->window_lock, flags); in ni_ao_win_inw()
862 spin_unlock_irqrestore(&devpriv->window_lock, flags); in ni_ao_win_inw()
872 * so this is actually quite fast--- If you must wrap another function around
892 struct ni_private *devpriv = dev->private; in ni_sync_ai_dma()
893 struct comedi_subdevice *s = dev->read_subdev; in ni_sync_ai_dma()
896 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in ni_sync_ai_dma()
897 if (devpriv->ai_mite_chan) in ni_sync_ai_dma()
898 mite_sync_dma(devpriv->ai_mite_chan, s); in ni_sync_ai_dma()
899 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_sync_ai_dma()
904 struct ni_private *devpriv = dev->private; in ni_ai_drain_dma()
910 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in ni_ai_drain_dma()
911 if (devpriv->ai_mite_chan) { in ni_ai_drain_dma()
915 mite_bytes_in_transit(devpriv->ai_mite_chan) == 0) in ni_ai_drain_dma()
920 dev_err(dev->class_dev, "timed out\n"); in ni_ai_drain_dma()
921 dev_err(dev->class_dev, in ni_ai_drain_dma()
923 mite_bytes_in_transit(devpriv->ai_mite_chan), in ni_ai_drain_dma()
925 retval = -1; in ni_ai_drain_dma()
928 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_ai_drain_dma()
947 * If we poll too often, the pci bus activity seems in ni_ao_wait_for_dma_load()
953 dev_err(dev->class_dev, "timed out waiting for dma load\n"); in ni_ao_wait_for_dma_load()
954 return -EPIPE; in ni_ao_wait_for_dma_load()
965 struct ni_private *devpriv = dev->private; in ni_ao_fifo_load()
973 if (devpriv->is_6xxx) { in ni_ao_fifo_load()
976 if (!devpriv->is_6711) { in ni_ao_fifo_load()
1007 const struct ni_board_struct *board = dev->board_ptr; in ni_ao_fifo_half_empty()
1013 s->async->events |= COMEDI_CB_OVERFLOW; in ni_ao_fifo_half_empty()
1018 if (nsamples > board->ao_fifo_depth / 2) in ni_ao_fifo_half_empty()
1019 nsamples = board->ao_fifo_depth / 2; in ni_ao_fifo_half_empty()
1029 const struct ni_board_struct *board = dev->board_ptr; in ni_ao_prep_fifo()
1030 struct ni_private *devpriv = dev->private; in ni_ao_prep_fifo()
1036 if (devpriv->is_6xxx) in ni_ao_prep_fifo()
1045 if (nsamples > board->ao_fifo_depth) in ni_ao_prep_fifo()
1046 nsamples = board->ao_fifo_depth; in ni_ao_prep_fifo()
1056 struct ni_private *devpriv = dev->private; in ni_ai_fifo_read()
1057 struct comedi_async *async = s->async; in ni_ai_fifo_read()
1062 if (devpriv->is_611x) { in ni_ai_fifo_read()
1077 } else if (devpriv->is_6143) { in ni_ai_fifo_read()
1099 if (n > ARRAY_SIZE(devpriv->ai_fifo_buffer)) { in ni_ai_fifo_read()
1100 dev_err(dev->class_dev, in ni_ai_fifo_read()
1102 async->events |= COMEDI_CB_ERROR; in ni_ai_fifo_read()
1106 devpriv->ai_fifo_buffer[i] = in ni_ai_fifo_read()
1109 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, n); in ni_ai_fifo_read()
1115 const struct ni_board_struct *board = dev->board_ptr; in ni_handle_fifo_half_full()
1116 struct comedi_subdevice *s = dev->read_subdev; in ni_handle_fifo_half_full()
1119 n = board->ai_fifo_depth / 2; in ni_handle_fifo_half_full()
1128 struct ni_private *devpriv = dev->private; in ni_handle_fifo_dregs()
1129 struct comedi_subdevice *s = dev->read_subdev; in ni_handle_fifo_dregs()
1134 if (devpriv->is_611x) { in ni_handle_fifo_dregs()
1145 } else if (devpriv->is_6143) { in ni_handle_fifo_dregs()
1173 i < ARRAY_SIZE(devpriv->ai_fifo_buffer); i++) { in ni_handle_fifo_dregs()
1178 devpriv->ai_fifo_buffer[i] = in ni_handle_fifo_dregs()
1181 comedi_buf_write_samples(s, devpriv->ai_fifo_buffer, i); in ni_handle_fifo_dregs()
1188 struct ni_private *devpriv = dev->private; in get_last_sample_611x()
1189 struct comedi_subdevice *s = dev->read_subdev; in get_last_sample_611x()
1193 if (!devpriv->is_611x) in get_last_sample_611x()
1206 struct ni_private *devpriv = dev->private; in get_last_sample_6143()
1207 struct comedi_subdevice *s = dev->read_subdev; in get_last_sample_6143()
1211 if (!devpriv->is_6143) in get_last_sample_6143()
1228 struct comedi_subdevice *s = dev->read_subdev; in shutdown_ai_command()
1237 s->async->events |= COMEDI_CB_EOA; in shutdown_ai_command()
1242 struct ni_private *devpriv = dev->private; in ni_handle_eos()
1244 if (devpriv->aimode == AIMODE_SCAN) { in ni_handle_eos()
1251 if ((s->async->events & COMEDI_CB_EOS)) in ni_handle_eos()
1257 s->async->events |= COMEDI_CB_EOS; in ni_handle_eos()
1261 if (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS) in ni_handle_eos()
1269 struct ni_private *devpriv = dev->private; in handle_gpct_interrupt()
1272 s = &dev->subdevices[NI_GPCT_SUBDEV(counter_index)]; in handle_gpct_interrupt()
1274 ni_tio_handle_interrupt(&devpriv->counter_dev->counters[counter_index], in handle_gpct_interrupt()
1302 struct comedi_cmd *cmd = &s->async->cmd; in handle_a_interrupt()
1308 dev_err(dev->class_dev, "Card removed?\n"); in handle_a_interrupt()
1314 s->async->events |= COMEDI_CB_ERROR; in handle_a_interrupt()
1318 dev_err(dev->class_dev, "ai error a_status=%04x\n", in handle_a_interrupt()
1323 s->async->events |= COMEDI_CB_ERROR; in handle_a_interrupt()
1325 s->async->events |= COMEDI_CB_OVERFLOW; in handle_a_interrupt()
1329 if (cmd->stop_src == TRIG_COUNT) in handle_a_interrupt()
1384 dev_err(dev->class_dev, in handle_b_interrupt()
1387 s->async->events |= COMEDI_CB_OVERFLOW; in handle_b_interrupt()
1390 if (s->async->cmd.stop_src != TRIG_NONE && in handle_b_interrupt()
1392 s->async->events |= COMEDI_CB_EOA; in handle_b_interrupt()
1400 dev_err(dev->class_dev, "AO buffer underrun\n"); in handle_b_interrupt()
1404 s->async->events |= COMEDI_CB_OVERFLOW; in handle_b_interrupt()
1414 struct ni_private *devpriv = dev->private; in ni_ai_munge()
1415 struct comedi_async *async = s->async; in ni_ai_munge()
1416 struct comedi_cmd *cmd = &async->cmd; in ni_ai_munge()
1428 if (s->subdev_flags & SDF_LSAMPL) in ni_ai_munge()
1433 if (s->subdev_flags & SDF_LSAMPL) in ni_ai_munge()
1434 larray[i] += devpriv->ai_offset[chan_index]; in ni_ai_munge()
1436 array[i] += devpriv->ai_offset[chan_index]; in ni_ai_munge()
1438 chan_index %= cmd->chanlist_len; in ni_ai_munge()
1446 struct ni_private *devpriv = dev->private; in ni_ai_setup_MITE_dma()
1447 struct comedi_subdevice *s = dev->read_subdev; in ni_ai_setup_MITE_dma()
1456 comedi_buf_write_alloc(s, s->async->prealloc_bufsz); in ni_ai_setup_MITE_dma()
1458 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in ni_ai_setup_MITE_dma()
1459 if (!devpriv->ai_mite_chan) { in ni_ai_setup_MITE_dma()
1460 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_ai_setup_MITE_dma()
1461 return -EIO; in ni_ai_setup_MITE_dma()
1464 if (devpriv->is_611x || devpriv->is_6143) in ni_ai_setup_MITE_dma()
1465 mite_prep_dma(devpriv->ai_mite_chan, 32, 16); in ni_ai_setup_MITE_dma()
1466 else if (devpriv->is_628x) in ni_ai_setup_MITE_dma()
1467 mite_prep_dma(devpriv->ai_mite_chan, 32, 32); in ni_ai_setup_MITE_dma()
1469 mite_prep_dma(devpriv->ai_mite_chan, 16, 16); in ni_ai_setup_MITE_dma()
1472 mite_dma_arm(devpriv->ai_mite_chan); in ni_ai_setup_MITE_dma()
1473 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_ai_setup_MITE_dma()
1480 struct ni_private *devpriv = dev->private; in ni_ao_setup_MITE_dma()
1481 struct comedi_subdevice *s = dev->write_subdev; in ni_ao_setup_MITE_dma()
1490 comedi_buf_read_alloc(s, s->async->prealloc_bufsz); in ni_ao_setup_MITE_dma()
1492 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in ni_ao_setup_MITE_dma()
1493 if (devpriv->ao_mite_chan) { in ni_ao_setup_MITE_dma()
1494 if (devpriv->is_611x || devpriv->is_6713) { in ni_ao_setup_MITE_dma()
1495 mite_prep_dma(devpriv->ao_mite_chan, 32, 32); in ni_ao_setup_MITE_dma()
1502 mite_prep_dma(devpriv->ao_mite_chan, 16, 32); in ni_ao_setup_MITE_dma()
1504 mite_dma_arm(devpriv->ao_mite_chan); in ni_ao_setup_MITE_dma()
1506 retval = -EIO; in ni_ao_setup_MITE_dma()
1508 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_ao_setup_MITE_dma()
1522 struct ni_private *devpriv = dev->private; in ni_ai_reset()
1535 if (!devpriv->is_6143) in ni_ai_reset()
1544 /* generate FIFO interrupts on non-empty */ in ni_ai_reset()
1555 if (devpriv->is_611x) { in ni_ai_reset()
1557 } else if (devpriv->is_6143) { in ni_ai_reset()
1561 if (devpriv->is_622x) in ni_ai_reset()
1592 spin_lock_irqsave(&dev->spinlock, flags); in ni_ai_poll()
1599 spin_unlock_irqrestore(&dev->spinlock, flags); in ni_ai_poll()
1617 dev_err(dev->class_dev, "timeout loading channel/gain list\n"); in ni_prime_channelgain_list()
1624 const struct ni_board_struct *board = dev->board_ptr; in ni_m_series_load_channelgain_list()
1625 struct ni_private *devpriv = dev->private; in ni_m_series_load_channelgain_list()
1638 range_code = ni_gainlkup[board->gainlkup][range]; in ni_m_series_load_channelgain_list()
1643 devpriv->ai_calib_source; in ni_m_series_load_channelgain_list()
1660 range_code = ni_gainlkup[board->gainlkup][range]; in ni_m_series_load_channelgain_list()
1661 devpriv->ai_offset[i] = 0; in ni_m_series_load_channelgain_list()
1678 if (i == n_chan - 1) in ni_m_series_load_channelgain_list()
1696 * bits 15-9: same
1698 * bits 0-3: gain. This is 4 bits instead of 3 for the other boards
1699 * 1001 gain=0.1 (+/- 50)
1709 * bits 12-14: Channel Type
1715 * bits 0-2: channel
1716 * valid channels are 0-3
1722 const struct ni_board_struct *board = dev->board_ptr; in ni_load_channelgain_list()
1723 struct ni_private *devpriv = dev->private; in ni_load_channelgain_list()
1724 unsigned int offset = (s->maxdata + 1) >> 1; in ni_load_channelgain_list()
1730 if (devpriv->is_m_series) { in ni_load_channelgain_list()
1734 if (n_chan == 1 && !devpriv->is_611x && !devpriv->is_6143) { in ni_load_channelgain_list()
1735 if (devpriv->changain_state && in ni_load_channelgain_list()
1736 devpriv->changain_spec == list[0]) { in ni_load_channelgain_list()
1740 devpriv->changain_state = 1; in ni_load_channelgain_list()
1741 devpriv->changain_spec = list[0]; in ni_load_channelgain_list()
1743 devpriv->changain_state = 0; in ni_load_channelgain_list()
1749 if (devpriv->is_6143) { in ni_load_channelgain_list()
1751 !devpriv->ai_calib_source_enabled) { in ni_load_channelgain_list()
1753 ni_writew(dev, devpriv->ai_calib_source | in ni_load_channelgain_list()
1756 ni_writew(dev, devpriv->ai_calib_source, in ni_load_channelgain_list()
1758 devpriv->ai_calib_source_enabled = 1; in ni_load_channelgain_list()
1762 devpriv->ai_calib_source_enabled) { in ni_load_channelgain_list()
1764 ni_writew(dev, devpriv->ai_calib_source | in ni_load_channelgain_list()
1767 ni_writew(dev, devpriv->ai_calib_source, in ni_load_channelgain_list()
1769 devpriv->ai_calib_source_enabled = 0; in ni_load_channelgain_list()
1776 if (!devpriv->is_6143 && (list[i] & CR_ALT_SOURCE)) in ni_load_channelgain_list()
1777 chan = devpriv->ai_calib_source; in ni_load_channelgain_list()
1785 range = ni_gainlkup[board->gainlkup][range]; in ni_load_channelgain_list()
1786 if (devpriv->is_611x) in ni_load_channelgain_list()
1787 devpriv->ai_offset[i] = offset; in ni_load_channelgain_list()
1789 devpriv->ai_offset[i] = (range & 0x100) ? 0 : offset; in ni_load_channelgain_list()
1793 if (devpriv->is_611x) in ni_load_channelgain_list()
1797 if (devpriv->is_611x) in ni_load_channelgain_list()
1799 else if (devpriv->is_6143) in ni_load_channelgain_list()
1819 if (!devpriv->is_6143) { in ni_load_channelgain_list()
1822 if (i == n_chan - 1) in ni_load_channelgain_list()
1832 if (!devpriv->is_611x && !devpriv->is_6143) in ni_load_channelgain_list()
1841 struct ni_private *devpriv = dev->private; in ni_ai_insn_read()
1842 unsigned int mask = s->maxdata; in ni_ai_insn_read()
1847 ni_load_channelgain_list(dev, s, 1, &insn->chanspec); in ni_ai_insn_read()
1851 signbits = devpriv->ai_offset[0]; in ni_ai_insn_read()
1852 if (devpriv->is_611x) { in ni_ai_insn_read()
1858 for (n = 0; n < insn->n; n++) { in ni_ai_insn_read()
1861 /* The 611x has screwy 32-bit FIFOs. */ in ni_ai_insn_read()
1880 dev_err(dev->class_dev, "timeout\n"); in ni_ai_insn_read()
1881 return -ETIME; in ni_ai_insn_read()
1886 } else if (devpriv->is_6143) { in ni_ai_insn_read()
1887 for (n = 0; n < insn->n; n++) { in ni_ai_insn_read()
1892 * The 6143 has 32-bit FIFOs. You need to strobe a in ni_ai_insn_read()
1909 dev_err(dev->class_dev, "timeout\n"); in ni_ai_insn_read()
1910 return -ETIME; in ni_ai_insn_read()
1915 for (n = 0; n < insn->n; n++) { in ni_ai_insn_read()
1924 dev_err(dev->class_dev, "timeout\n"); in ni_ai_insn_read()
1925 return -ETIME; in ni_ai_insn_read()
1927 if (devpriv->is_m_series) { in ni_ai_insn_read()
1938 return insn->n; in ni_ai_insn_read()
1944 struct ni_private *devpriv = dev->private; in ni_ns_to_timer()
1950 divider = DIV_ROUND_CLOSEST(nanosec, devpriv->clock_ns); in ni_ns_to_timer()
1953 divider = (nanosec) / devpriv->clock_ns; in ni_ns_to_timer()
1956 divider = DIV_ROUND_UP(nanosec, devpriv->clock_ns); in ni_ns_to_timer()
1959 return divider - 1; in ni_ns_to_timer()
1964 struct ni_private *devpriv = dev->private; in ni_timer_to_ns()
1966 return devpriv->clock_ns * (timer + 1); in ni_timer_to_ns()
1977 if (cmd->stop_arg > 0 && cmd->stop_arg < max_count) in ni_cmd_set_mite_transfer()
1978 nbytes = cmd->stop_arg; in ni_cmd_set_mite_transfer()
1981 if (nbytes > sdev->async->prealloc_bufsz) { in ni_cmd_set_mite_transfer()
1982 if (cmd->stop_arg > 0) in ni_cmd_set_mite_transfer()
1983 dev_err(sdev->device->class_dev, in ni_cmd_set_mite_transfer()
1992 nbytes = sdev->async->prealloc_bufsz; in ni_cmd_set_mite_transfer()
1997 dev_err(sdev->device->class_dev, in ni_cmd_set_mite_transfer()
2006 const struct ni_board_struct *board = dev->board_ptr; in ni_min_ai_scan_period_ns()
2007 struct ni_private *devpriv = dev->private; in ni_min_ai_scan_period_ns()
2009 /* simultaneously-sampled inputs */ in ni_min_ai_scan_period_ns()
2010 if (devpriv->is_611x || devpriv->is_6143) in ni_min_ai_scan_period_ns()
2011 return board->ai_speed; in ni_min_ai_scan_period_ns()
2014 return board->ai_speed * num_channels; in ni_min_ai_scan_period_ns()
2020 const struct ni_board_struct *board = dev->board_ptr; in ni_ai_cmdtest()
2021 struct ni_private *devpriv = dev->private; in ni_ai_cmdtest()
2023 unsigned int sources; in ni_ai_cmdtest() local
2027 err |= comedi_check_trigger_src(&cmd->start_src, in ni_ai_cmdtest()
2029 err |= comedi_check_trigger_src(&cmd->scan_begin_src, in ni_ai_cmdtest()
2032 sources = TRIG_TIMER | TRIG_EXT; in ni_ai_cmdtest()
2033 if (devpriv->is_611x || devpriv->is_6143) in ni_ai_cmdtest()
2034 sources |= TRIG_NOW; in ni_ai_cmdtest()
2035 err |= comedi_check_trigger_src(&cmd->convert_src, sources); in ni_ai_cmdtest()
2037 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT); in ni_ai_cmdtest()
2038 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE); in ni_ai_cmdtest()
2043 /* Step 2a : make sure trigger sources are unique */ in ni_ai_cmdtest()
2045 err |= comedi_check_trigger_is_unique(cmd->start_src); in ni_ai_cmdtest()
2046 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src); in ni_ai_cmdtest()
2047 err |= comedi_check_trigger_is_unique(cmd->convert_src); in ni_ai_cmdtest()
2048 err |= comedi_check_trigger_is_unique(cmd->stop_src); in ni_ai_cmdtest()
2057 switch (cmd->start_src) { in ni_ai_cmdtest()
2060 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0); in ni_ai_cmdtest()
2063 err |= ni_check_trigger_arg_roffs(CR_CHAN(cmd->start_arg), in ni_ai_cmdtest()
2065 &devpriv->routing_tables, 1); in ni_ai_cmdtest()
2069 if (cmd->scan_begin_src == TRIG_TIMER) { in ni_ai_cmdtest()
2070 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg, in ni_ai_cmdtest()
2071 ni_min_ai_scan_period_ns(dev, cmd->chanlist_len)); in ni_ai_cmdtest()
2072 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg, in ni_ai_cmdtest()
2073 devpriv->clock_ns * in ni_ai_cmdtest()
2075 } else if (cmd->scan_begin_src == TRIG_EXT) { in ni_ai_cmdtest()
2077 err |= ni_check_trigger_arg_roffs(CR_CHAN(cmd->scan_begin_arg), in ni_ai_cmdtest()
2079 &devpriv->routing_tables, 1); in ni_ai_cmdtest()
2081 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, 0); in ni_ai_cmdtest()
2084 if (cmd->convert_src == TRIG_TIMER) { in ni_ai_cmdtest()
2085 if (devpriv->is_611x || devpriv->is_6143) { in ni_ai_cmdtest()
2086 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, in ni_ai_cmdtest()
2089 err |= comedi_check_trigger_arg_min(&cmd->convert_arg, in ni_ai_cmdtest()
2090 board->ai_speed); in ni_ai_cmdtest()
2091 err |= comedi_check_trigger_arg_max(&cmd->convert_arg, in ni_ai_cmdtest()
2092 devpriv->clock_ns * in ni_ai_cmdtest()
2095 } else if (cmd->convert_src == TRIG_EXT) { in ni_ai_cmdtest()
2097 err |= ni_check_trigger_arg_roffs(CR_CHAN(cmd->convert_arg), in ni_ai_cmdtest()
2099 &devpriv->routing_tables, 1); in ni_ai_cmdtest()
2100 } else if (cmd->convert_src == TRIG_NOW) { in ni_ai_cmdtest()
2101 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0); in ni_ai_cmdtest()
2104 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg, in ni_ai_cmdtest()
2105 cmd->chanlist_len); in ni_ai_cmdtest()
2107 if (cmd->stop_src == TRIG_COUNT) { in ni_ai_cmdtest()
2110 if (devpriv->is_611x) in ni_ai_cmdtest()
2111 max_count -= num_adc_stages_611x; in ni_ai_cmdtest()
2112 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, max_count); in ni_ai_cmdtest()
2113 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1); in ni_ai_cmdtest()
2116 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0); in ni_ai_cmdtest()
2124 if (cmd->scan_begin_src == TRIG_TIMER) { in ni_ai_cmdtest()
2125 unsigned int tmp = cmd->scan_begin_arg; in ni_ai_cmdtest()
2127 cmd->scan_begin_arg = in ni_ai_cmdtest()
2129 cmd->scan_begin_arg, in ni_ai_cmdtest()
2130 cmd->flags)); in ni_ai_cmdtest()
2131 if (tmp != cmd->scan_begin_arg) in ni_ai_cmdtest()
2134 if (cmd->convert_src == TRIG_TIMER) { in ni_ai_cmdtest()
2135 if (!devpriv->is_611x && !devpriv->is_6143) { in ni_ai_cmdtest()
2136 unsigned int tmp = cmd->convert_arg; in ni_ai_cmdtest()
2138 cmd->convert_arg = in ni_ai_cmdtest()
2140 cmd->convert_arg, in ni_ai_cmdtest()
2141 cmd->flags)); in ni_ai_cmdtest()
2142 if (tmp != cmd->convert_arg) in ni_ai_cmdtest()
2144 if (cmd->scan_begin_src == TRIG_TIMER && in ni_ai_cmdtest()
2145 cmd->scan_begin_arg < in ni_ai_cmdtest()
2146 cmd->convert_arg * cmd->scan_end_arg) { in ni_ai_cmdtest()
2147 cmd->scan_begin_arg = in ni_ai_cmdtest()
2148 cmd->convert_arg * cmd->scan_end_arg; in ni_ai_cmdtest()
2164 struct ni_private *devpriv = dev->private; in ni_ai_inttrig()
2165 struct comedi_cmd *cmd = &s->async->cmd; in ni_ai_inttrig()
2167 if (trig_num != cmd->start_arg) in ni_ai_inttrig()
2168 return -EINVAL; in ni_ai_inttrig()
2170 ni_stc_writew(dev, NISTC_AI_CMD2_START1_PULSE | devpriv->ai_cmd2, in ni_ai_inttrig()
2172 s->async->inttrig = NULL; in ni_ai_inttrig()
2179 struct ni_private *devpriv = dev->private; in ni_ai_cmd()
2180 const struct comedi_cmd *cmd = &s->async->cmd; in ni_ai_cmd()
2189 if (dev->irq == 0) { in ni_ai_cmd()
2190 dev_err(dev->class_dev, "cannot run command without an irq\n"); in ni_ai_cmd()
2191 return -EIO; in ni_ai_cmd()
2195 ni_load_channelgain_list(dev, s, cmd->chanlist_len, cmd->chanlist); in ni_ai_cmd()
2204 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_ENA; in ni_ai_cmd()
2205 ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG); in ni_ai_cmd()
2208 switch (cmd->start_src) { in ni_ai_cmd()
2217 CR_CHAN(cmd->start_arg), in ni_ai_cmd()
2219 &devpriv->routing_tables, 1)); in ni_ai_cmd()
2221 if (cmd->start_arg & CR_INVERT) in ni_ai_cmd()
2223 if (cmd->start_arg & CR_EDGE) in ni_ai_cmd()
2234 if (cmd->chanlist_len == 1 || devpriv->is_611x || devpriv->is_6143) { in ni_ai_cmd()
2245 devpriv->ai_cmd2 = 0; in ni_ai_cmd()
2246 switch (cmd->stop_src) { in ni_ai_cmd()
2248 stop_count = cmd->stop_arg - 1; in ni_ai_cmd()
2250 if (devpriv->is_611x) { in ni_ai_cmd()
2265 devpriv->ai_cmd2 |= NISTC_AI_CMD2_END_ON_EOS; in ni_ai_cmd()
2271 if (cmd->chanlist_len > 1) in ni_ai_cmd()
2290 switch (cmd->scan_begin_src) { in ni_ai_cmd()
2315 timer = ni_ns_to_timer(dev, cmd->scan_begin_arg, in ni_ai_cmd()
2321 if (cmd->scan_begin_arg & CR_EDGE) in ni_ai_cmd()
2323 if (cmd->scan_begin_arg & CR_INVERT) /* falling edge */ in ni_ai_cmd()
2325 if (cmd->scan_begin_src != cmd->convert_src || in ni_ai_cmd()
2326 (cmd->scan_begin_arg & ~CR_EDGE) != in ni_ai_cmd()
2327 (cmd->convert_arg & ~CR_EDGE)) in ni_ai_cmd()
2332 CR_CHAN(cmd->scan_begin_arg), in ni_ai_cmd()
2334 &devpriv->routing_tables, 1)); in ni_ai_cmd()
2339 switch (cmd->convert_src) { in ni_ai_cmd()
2342 if (cmd->convert_arg == 0 || cmd->convert_src == TRIG_NOW) in ni_ai_cmd()
2345 timer = ni_ns_to_timer(dev, cmd->convert_arg, in ni_ai_cmd()
2364 CR_CHAN(cmd->convert_arg), in ni_ai_cmd()
2366 &devpriv->routing_tables, 1)); in ni_ai_cmd()
2367 if ((cmd->convert_arg & CR_INVERT) == 0) in ni_ai_cmd()
2378 if (dev->irq) { in ni_ai_cmd()
2387 if ((cmd->flags & CMDF_WAKE_EOS) || in ni_ai_cmd()
2388 (devpriv->ai_cmd2 & NISTC_AI_CMD2_END_ON_EOS)) { in ni_ai_cmd()
2389 /* wake on end-of-scan */ in ni_ai_cmd()
2390 devpriv->aimode = AIMODE_SCAN; in ni_ai_cmd()
2392 devpriv->aimode = AIMODE_HALF_FULL; in ni_ai_cmd()
2395 switch (devpriv->aimode) { in ni_ai_cmd()
2397 /* FIFO interrupts and DMA requests on half-full */ in ni_ai_cmd()
2407 /* generate FIFO interrupts on non-empty */ in ni_ai_cmd()
2439 switch (cmd->scan_begin_src) { in ni_ai_cmd()
2465 if (cmd->start_src == TRIG_NOW) { in ni_ai_cmd()
2467 devpriv->ai_cmd2, in ni_ai_cmd()
2469 s->async->inttrig = NULL; in ni_ai_cmd()
2470 } else if (cmd->start_src == TRIG_EXT) { in ni_ai_cmd()
2471 s->async->inttrig = NULL; in ni_ai_cmd()
2473 s->async->inttrig = ni_ai_inttrig; in ni_ai_cmd()
2483 const struct ni_board_struct *board = dev->board_ptr; in ni_ai_insn_config()
2484 struct ni_private *devpriv = dev->private; in ni_ai_insn_config()
2486 if (insn->n < 1) in ni_ai_insn_config()
2487 return -EINVAL; in ni_ai_insn_config()
2491 if (devpriv->is_m_series) { in ni_ai_insn_config()
2493 return -EINVAL; in ni_ai_insn_config()
2494 devpriv->ai_calib_source = data[1]; in ni_ai_insn_config()
2495 } else if (devpriv->is_6143) { in ni_ai_insn_config()
2500 devpriv->ai_calib_source = calib_source; in ni_ai_insn_config()
2510 return -EINVAL; in ni_ai_insn_config()
2511 devpriv->ai_calib_source = calib_source; in ni_ai_insn_config()
2512 if (devpriv->is_611x) { in ni_ai_insn_config()
2522 if (devpriv->is_611x || devpriv->is_6143) in ni_ai_insn_config()
2525 data[2] = board->ai_speed; in ni_ai_insn_config()
2531 return -EINVAL; in ni_ai_insn_config()
2538 struct comedi_cmd *cmd = &s->async->cmd; in ni_ao_munge()
2547 unsigned int range = CR_RANGE(cmd->chanlist[chan_index]); in ni_ao_munge()
2563 chan_index %= cmd->chanlist_len; in ni_ao_munge()
2572 struct ni_private *devpriv = dev->private; in ni_m_series_ao_config_chanlist()
2580 for (i = 0; i < s->n_chan; ++i) { in ni_m_series_ao_config_chanlist()
2581 devpriv->ao_conf[i] &= ~NI_M_AO_CFG_BANK_UPDATE_TIMED; in ni_m_series_ao_config_chanlist()
2582 ni_writeb(dev, devpriv->ao_conf[i], in ni_m_series_ao_config_chanlist()
2592 krange = s->range_table->range + range; in ni_m_series_ao_config_chanlist()
2595 switch (krange->max - krange->min) { in ni_m_series_ao_config_chanlist()
2615 dev_err(dev->class_dev, in ni_m_series_ao_config_chanlist()
2619 switch (krange->max + krange->min) { in ni_m_series_ao_config_chanlist()
2627 dev_err(dev->class_dev, in ni_m_series_ao_config_chanlist()
2634 devpriv->ao_conf[chan] = conf; in ni_m_series_ao_config_chanlist()
2645 struct ni_private *devpriv = dev->private; in ni_old_ao_config_chanlist()
2659 invert = (s->maxdata + 1) >> 1; in ni_old_ao_config_chanlist()
2676 devpriv->ao_conf[chan] = conf; in ni_old_ao_config_chanlist()
2686 struct ni_private *devpriv = dev->private; in ni_ao_config_chanlist()
2688 if (devpriv->is_m_series) in ni_ao_config_chanlist()
2700 struct ni_private *devpriv = dev->private; in ni_ao_insn_write()
2701 unsigned int chan = CR_CHAN(insn->chanspec); in ni_ao_insn_write()
2702 unsigned int range = CR_RANGE(insn->chanspec); in ni_ao_insn_write()
2706 if (devpriv->is_6xxx) { in ni_ao_insn_write()
2710 } else if (devpriv->is_m_series) { in ni_ao_insn_write()
2716 ni_ao_config_chanlist(dev, s, &insn->chanspec, 1, 0); in ni_ao_insn_write()
2718 for (i = 0; i < insn->n; i++) { in ni_ao_insn_write()
2721 s->readback[chan] = val; in ni_ao_insn_write()
2723 if (devpriv->is_6xxx) { in ni_ao_insn_write()
2731 } else if (devpriv->is_m_series) { in ni_ao_insn_write()
2733 * M-series boards use offset binary values for in ni_ao_insn_write()
2739 * Non-M series boards need two's complement values in ni_ao_insn_write()
2749 return insn->n; in ni_ao_insn_write()
2765 struct ni_private *devpriv = dev->private; in ni_ao_arm()
2775 if (!devpriv->ao_needs_arming) { in ni_ao_arm()
2776 dev_dbg(dev->class_dev, "%s: device does not need arming!\n", in ni_ao_arm()
2778 return -EINVAL; in ni_ao_arm()
2781 devpriv->ao_needs_arming = 0; in ni_ao_arm()
2788 if (devpriv->is_6xxx) in ni_ao_arm()
2799 return -EPIPE; in ni_ao_arm()
2804 ni_stc_writew(dev, devpriv->ao_mode3 | NISTC_AO_MODE3_NOT_AN_UPDATE, in ni_ao_arm()
2806 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG); in ni_ao_arm()
2815 dev_err(dev->class_dev, in ni_ao_arm()
2817 return -EIO; in ni_ao_arm()
2830 devpriv->ao_cmd1, in ni_ao_arm()
2840 const struct ni_board_struct *board = dev->board_ptr; in ni_ao_insn_config()
2841 struct ni_private *devpriv = dev->private; in ni_ao_insn_config()
2849 board->ao_fifo_depth); in ni_ao_insn_config()
2851 if (devpriv->mite) in ni_ao_insn_config()
2852 data[2] += devpriv->mite->fifo_size; in ni_ao_insn_config()
2858 return -EINVAL; in ni_ao_insn_config()
2866 data[1] = board->ao_speed * data[3]; in ni_ao_insn_config()
2873 return -EINVAL; in ni_ao_insn_config()
2880 struct ni_private *devpriv = dev->private; in ni_ao_inttrig()
2881 struct comedi_cmd *cmd = &s->async->cmd; in ni_ao_inttrig()
2885 * Require trig_num == cmd->start_arg when cmd->start_src == TRIG_INT. in ni_ao_inttrig()
2887 * cmd->start_src != TRIG_INT (i.e. when cmd->start_src == TRIG_EXT); in ni_ao_inttrig()
2888 * in that case, the internal trigger is being used as a pre-trigger in ni_ao_inttrig()
2891 if (!(trig_num == cmd->start_arg || in ni_ao_inttrig()
2892 (trig_num == 0 && cmd->start_src != TRIG_INT))) in ni_ao_inttrig()
2893 return -EINVAL; in ni_ao_inttrig()
2899 s->async->inttrig = NULL; in ni_ao_inttrig()
2901 if (devpriv->ao_needs_arming) { in ni_ao_inttrig()
2908 ni_stc_writew(dev, NISTC_AO_CMD2_START1_PULSE | devpriv->ao_cmd2, in ni_ao_inttrig()
2916 * Organized similar to NI-STC and MHDDK examples.
2917 * ni_ao_cmd is broken out into configuration sub-routines for clarity.
2923 const struct ni_board_struct *board = dev->board_ptr; in ni_ao_cmd_personalize()
2929 /* fast CPU interface--only eseries */ in ni_ao_cmd_personalize()
2945 (board->ao_fifo_depth ? in ni_ao_cmd_personalize()
2953 * sure if e-series all have duals... in ni_ao_cmd_personalize()
2960 if (devpriv->is_m_series) in ni_ao_cmd_personalize()
2971 struct ni_private *devpriv = dev->private; in ni_ao_cmd_set_trigger()
2977 if (cmd->stop_src == TRIG_NONE) { in ni_ao_cmd_set_trigger()
2978 devpriv->ao_mode1 |= NISTC_AO_MODE1_CONTINUOUS; in ni_ao_cmd_set_trigger()
2979 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_TRIGGER_ONCE; in ni_ao_cmd_set_trigger()
2981 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_CONTINUOUS; in ni_ao_cmd_set_trigger()
2982 devpriv->ao_mode1 |= NISTC_AO_MODE1_TRIGGER_ONCE; in ni_ao_cmd_set_trigger()
2984 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG); in ni_ao_cmd_set_trigger()
2986 if (cmd->start_src == TRIG_INT) { in ni_ao_cmd_set_trigger()
2992 CR_CHAN(cmd->start_arg), in ni_ao_cmd_set_trigger()
2994 &devpriv->routing_tables, 1)); in ni_ao_cmd_set_trigger()
2996 /* 0=active high, 1=active low. see daq-stc 3-24 (p186) */ in ni_ao_cmd_set_trigger()
2997 if (cmd->start_arg & CR_INVERT) in ni_ao_cmd_set_trigger()
3000 if (cmd->start_arg & CR_EDGE) in ni_ao_cmd_set_trigger()
3009 devpriv->ao_mode3 &= ~NISTC_AO_MODE3_TRIG_LEN; in ni_ao_cmd_set_trigger()
3010 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG); in ni_ao_cmd_set_trigger()
3018 struct ni_private *devpriv = dev->private; in ni_ao_cmd_set_counters()
3024 * set_trigger above. It is unclear whether we really need to re-write in ni_ao_cmd_set_counters()
3025 * this register with these values. The mhddk examples for e-series in ni_ao_cmd_set_counters()
3026 * show writing this in both places, but the examples for m-series show in ni_ao_cmd_set_counters()
3029 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG); in ni_ao_cmd_set_counters()
3031 /* sync (upload number of buffer iterations -1) */ in ni_ao_cmd_set_counters()
3033 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_BC_INIT_LOAD_SRC; in ni_ao_cmd_set_counters()
3034 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG); in ni_ao_cmd_set_counters()
3043 /* sync (issue command to load number of buffer iterations -1) */ in ni_ao_cmd_set_counters()
3048 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_UC_INIT_LOAD_SRC; in ni_ao_cmd_set_counters()
3049 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG); in ni_ao_cmd_set_counters()
3060 unsigned int stop_arg = cmd->stop_arg > 0 ? in ni_ao_cmd_set_counters()
3061 (cmd->stop_arg & 0xffffff) : 0xffffff; in ni_ao_cmd_set_counters()
3063 if (devpriv->is_m_series) { in ni_ao_cmd_set_counters()
3065 * this is how the NI example code does it for m-series in ni_ao_cmd_set_counters()
3068 ni_stc_writel(dev, stop_arg - 1, NISTC_AO_UC_LOADA_REG); in ni_ao_cmd_set_counters()
3081 * sync (upload number of updates-1 in MISB) in ni_ao_cmd_set_counters()
3082 * --eseries only? in ni_ao_cmd_set_counters()
3084 ni_stc_writel(dev, stop_arg - 1, NISTC_AO_UC_LOADA_REG); in ni_ao_cmd_set_counters()
3094 struct ni_private *devpriv = dev->private; in ni_ao_cmd_set_update()
3099 * zero out these bit fields to be set below. Does an ao-reset do this in ni_ao_cmd_set_update()
3102 devpriv->ao_mode1 &= ~(NISTC_AO_MODE1_UI_SRC_MASK | in ni_ao_cmd_set_update()
3107 if (cmd->scan_begin_src == TRIG_TIMER) { in ni_ao_cmd_set_update()
3110 devpriv->ao_cmd2 &= ~NISTC_AO_CMD2_BC_GATE_ENA; in ni_ao_cmd_set_update()
3122 * devpriv->ao_mode1 &= ~( in ni_ao_cmd_set_update()
3140 trigvar = ni_ns_to_timer(dev, cmd->scan_begin_arg, in ni_ao_cmd_set_update()
3147 /* following line: 2-1 per STC */ in ni_ao_cmd_set_update()
3153 devpriv->ao_cmd2 |= NISTC_AO_CMD2_BC_GATE_ENA; in ni_ao_cmd_set_update()
3154 devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC( in ni_ao_cmd_set_update()
3156 CR_CHAN(cmd->scan_begin_arg), in ni_ao_cmd_set_update()
3158 &devpriv->routing_tables)); in ni_ao_cmd_set_update()
3159 if (cmd->scan_begin_arg & CR_INVERT) in ni_ao_cmd_set_update()
3160 devpriv->ao_mode1 |= NISTC_AO_MODE1_UPDATE_SRC_POLARITY; in ni_ao_cmd_set_update()
3163 ni_stc_writew(dev, devpriv->ao_cmd2, NISTC_AO_CMD2_REG); in ni_ao_cmd_set_update()
3164 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG); in ni_ao_cmd_set_update()
3165 devpriv->ao_mode2 &= ~(NISTC_AO_MODE2_UI_RELOAD_MODE(3) | in ni_ao_cmd_set_update()
3167 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG); in ni_ao_cmd_set_update()
3169 /* Configure DAQ-STC for Timed update mode */ in ni_ao_cmd_set_update()
3170 devpriv->ao_cmd1 |= NISTC_AO_CMD1_DAC1_UPDATE_MODE | in ni_ao_cmd_set_update()
3172 /* We are not using UPDATE2-->don't have to set DACx_Source_Select */ in ni_ao_cmd_set_update()
3173 ni_stc_writew(dev, devpriv->ao_cmd1, NISTC_AO_CMD1_REG); in ni_ao_cmd_set_update()
3181 struct ni_private *devpriv = dev->private; in ni_ao_cmd_set_channels()
3182 const struct comedi_cmd *cmd = &s->async->cmd; in ni_ao_cmd_set_channels()
3187 if (devpriv->is_6xxx) { in ni_ao_cmd_set_channels()
3191 for (i = 0; i < cmd->chanlist_len; ++i) { in ni_ao_cmd_set_channels()
3192 int chan = CR_CHAN(cmd->chanlist[i]); in ni_ao_cmd_set_channels()
3200 ni_ao_config_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len, 1); in ni_ao_cmd_set_channels()
3202 if (cmd->scan_end_arg > 1) { in ni_ao_cmd_set_channels()
3203 devpriv->ao_mode1 |= NISTC_AO_MODE1_MULTI_CHAN; in ni_ao_cmd_set_channels()
3204 bits = NISTC_AO_OUT_CTRL_CHANS(cmd->scan_end_arg - 1) in ni_ao_cmd_set_channels()
3208 devpriv->ao_mode1 &= ~NISTC_AO_MODE1_MULTI_CHAN; in ni_ao_cmd_set_channels()
3210 if (devpriv->is_m_series | devpriv->is_6xxx) in ni_ao_cmd_set_channels()
3214 CR_CHAN(cmd->chanlist[0])); in ni_ao_cmd_set_channels()
3217 ni_stc_writew(dev, devpriv->ao_mode1, NISTC_AO_MODE1_REG); in ni_ao_cmd_set_channels()
3226 struct ni_private *devpriv = dev->private; in ni_ao_cmd_set_stop_conditions()
3230 devpriv->ao_mode3 |= NISTC_AO_MODE3_STOP_ON_OVERRUN_ERR; in ni_ao_cmd_set_stop_conditions()
3231 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG); in ni_ao_cmd_set_stop_conditions()
3244 struct ni_private *devpriv = dev->private; in ni_ao_cmd_set_fifo_mode()
3248 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_MODE_MASK; in ni_ao_cmd_set_fifo_mode()
3250 devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF_F; in ni_ao_cmd_set_fifo_mode()
3252 devpriv->ao_mode2 |= NISTC_AO_MODE2_FIFO_MODE_HF; in ni_ao_cmd_set_fifo_mode()
3255 devpriv->ao_mode2 &= ~NISTC_AO_MODE2_FIFO_REXMIT_ENA; in ni_ao_cmd_set_fifo_mode()
3256 ni_stc_writew(dev, devpriv->ao_mode2, NISTC_AO_MODE2_REG); in ni_ao_cmd_set_fifo_mode()
3269 if (s->async->cmd.stop_src == TRIG_COUNT) in ni_ao_cmd_set_interrupts()
3273 s->async->inttrig = ni_ao_inttrig; in ni_ao_cmd_set_interrupts()
3278 struct ni_private *devpriv = dev->private; in ni_ao_cmd()
3279 const struct comedi_cmd *cmd = &s->async->cmd; in ni_ao_cmd()
3281 if (dev->irq == 0) { in ni_ao_cmd()
3282 dev_err(dev->class_dev, "cannot run command without an irq"); in ni_ao_cmd()
3283 return -EIO; in ni_ao_cmd()
3296 ni_cmd_set_mite_transfer(devpriv->ao_mite_ring, s, cmd, 0x00ffffff); in ni_ao_cmd()
3310 devpriv->ao_needs_arming = 1; in ni_ao_cmd()
3319 const struct ni_board_struct *board = dev->board_ptr; in ni_ao_cmdtest()
3320 struct ni_private *devpriv = dev->private; in ni_ao_cmdtest()
3326 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT); in ni_ao_cmdtest()
3327 err |= comedi_check_trigger_src(&cmd->scan_begin_src, in ni_ao_cmdtest()
3329 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW); in ni_ao_cmdtest()
3330 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT); in ni_ao_cmdtest()
3331 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE); in ni_ao_cmdtest()
3336 /* Step 2a : make sure trigger sources are unique */ in ni_ao_cmdtest()
3338 err |= comedi_check_trigger_is_unique(cmd->start_src); in ni_ao_cmdtest()
3339 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src); in ni_ao_cmdtest()
3340 err |= comedi_check_trigger_is_unique(cmd->stop_src); in ni_ao_cmdtest()
3349 switch (cmd->start_src) { in ni_ao_cmdtest()
3351 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0); in ni_ao_cmdtest()
3354 err |= ni_check_trigger_arg_roffs(CR_CHAN(cmd->start_arg), in ni_ao_cmdtest()
3356 &devpriv->routing_tables, 1); in ni_ao_cmdtest()
3360 if (cmd->scan_begin_src == TRIG_TIMER) { in ni_ao_cmdtest()
3361 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg, in ni_ao_cmdtest()
3362 board->ao_speed); in ni_ao_cmdtest()
3363 err |= comedi_check_trigger_arg_max(&cmd->scan_begin_arg, in ni_ao_cmdtest()
3364 devpriv->clock_ns * in ni_ao_cmdtest()
3367 err |= ni_check_trigger_arg(CR_CHAN(cmd->scan_begin_arg), in ni_ao_cmdtest()
3369 &devpriv->routing_tables); in ni_ao_cmdtest()
3372 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0); in ni_ao_cmdtest()
3373 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg, in ni_ao_cmdtest()
3374 cmd->chanlist_len); in ni_ao_cmdtest()
3375 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, 0x00ffffff); in ni_ao_cmdtest()
3381 if (cmd->scan_begin_src == TRIG_TIMER) { in ni_ao_cmdtest()
3382 tmp = cmd->scan_begin_arg; in ni_ao_cmdtest()
3383 cmd->scan_begin_arg = in ni_ao_cmdtest()
3385 cmd->scan_begin_arg, in ni_ao_cmdtest()
3386 cmd->flags)); in ni_ao_cmdtest()
3387 if (tmp != cmd->scan_begin_arg) in ni_ao_cmdtest()
3398 /* See 3.6.1.2 "Resetting", of DAQ-STC Technical Reference Manual */ in ni_ao_reset()
3401 * In the following, the "--sync" comments are meant to denote in ni_ao_reset()
3403 * DAQ-STC mostly in the order also described in the DAQ-STC. in ni_ao_reset()
3406 struct ni_private *devpriv = dev->private; in ni_ao_reset()
3410 /* --sync (reset AO) */ in ni_ao_reset()
3411 if (devpriv->is_m_series) in ni_ao_reset()
3412 /* following example in mhddk for m-series */ in ni_ao_reset()
3415 /*--sync (start config) */ in ni_ao_reset()
3418 /*--sync (Disarm) */ in ni_ao_reset()
3422 * --sync in ni_ao_reset()
3423 * (clear bunch of registers--mseries mhddk examples do not include in ni_ao_reset()
3426 devpriv->ao_cmd1 = 0; in ni_ao_reset()
3427 devpriv->ao_cmd2 = 0; in ni_ao_reset()
3428 devpriv->ao_mode1 = 0; in ni_ao_reset()
3429 devpriv->ao_mode2 = 0; in ni_ao_reset()
3430 if (devpriv->is_m_series) in ni_ao_reset()
3431 devpriv->ao_mode3 = NISTC_AO_MODE3_LAST_GATE_DISABLE; in ni_ao_reset()
3433 devpriv->ao_mode3 = 0; in ni_ao_reset()
3441 ni_stc_writew(dev, devpriv->ao_mode3, NISTC_AO_MODE3_REG); in ni_ao_reset()
3445 /*--sync (disable interrupts) */ in ni_ao_reset()
3448 /*--sync (ack) */ in ni_ao_reset()
3452 /*--not in DAQ-STC. which doc? */ in ni_ao_reset()
3453 if (devpriv->is_6xxx) { in ni_ao_reset()
3454 ni_ao_win_outw(dev, (1u << s->n_chan) - 1u, in ni_ao_reset()
3460 /*--end */ in ni_ao_reset()
3472 struct ni_private *devpriv = dev->private; in ni_dio_insn_config()
3479 devpriv->dio_control &= ~NISTC_DIO_CTRL_DIR_MASK; in ni_dio_insn_config()
3480 devpriv->dio_control |= NISTC_DIO_CTRL_DIR(s->io_bits); in ni_dio_insn_config()
3481 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG); in ni_dio_insn_config()
3483 return insn->n; in ni_dio_insn_config()
3491 struct ni_private *devpriv = dev->private; in ni_dio_insn_bits()
3495 devpriv->serial_interval_ns) in ni_dio_insn_bits()
3496 return -EBUSY; in ni_dio_insn_bits()
3499 devpriv->dio_output &= ~NISTC_DIO_OUT_PARALLEL_MASK; in ni_dio_insn_bits()
3500 devpriv->dio_output |= NISTC_DIO_OUT_PARALLEL(s->state); in ni_dio_insn_bits()
3501 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG); in ni_dio_insn_bits()
3506 return insn->n; in ni_dio_insn_bits()
3518 const struct ni_board_struct *board = dev->board_ptr; in ni_m_series_dio_insn_config()
3521 data[1] = board->dio_speed; in ni_m_series_dio_insn_config()
3530 ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG); in ni_m_series_dio_insn_config()
3532 return insn->n; in ni_m_series_dio_insn_config()
3541 ni_writel(dev, s->state, NI_M_DIO_REG); in ni_m_series_dio_insn_bits()
3545 return insn->n; in ni_m_series_dio_insn_bits()
3554 for (i = 0; i < cmd->chanlist_len; ++i) { in ni_cdio_check_chanlist()
3555 unsigned int chan = CR_CHAN(cmd->chanlist[i]); in ni_cdio_check_chanlist()
3558 return -EINVAL; in ni_cdio_check_chanlist()
3567 struct ni_private *devpriv = dev->private; in ni_cdio_cmdtest()
3573 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT); in ni_cdio_cmdtest()
3574 err |= comedi_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT); in ni_cdio_cmdtest()
3575 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW); in ni_cdio_cmdtest()
3576 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT); in ni_cdio_cmdtest()
3577 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE); in ni_cdio_cmdtest()
3582 /* Step 2a : make sure trigger sources are unique */ in ni_cdio_cmdtest()
3587 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0); in ni_cdio_cmdtest()
3593 err |= ni_check_trigger_arg(CR_CHAN(cmd->scan_begin_arg), in ni_cdio_cmdtest()
3595 &devpriv->routing_tables); in ni_cdio_cmdtest()
3596 if (CR_RANGE(cmd->scan_begin_arg) != 0 || in ni_cdio_cmdtest()
3597 CR_AREF(cmd->scan_begin_arg) != 0) in ni_cdio_cmdtest()
3598 err |= -EINVAL; in ni_cdio_cmdtest()
3600 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0); in ni_cdio_cmdtest()
3601 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg, in ni_cdio_cmdtest()
3602 cmd->chanlist_len); in ni_cdio_cmdtest()
3605 err |= comedi_check_trigger_arg_max(&cmd->stop_arg, in ni_cdio_cmdtest()
3606 s->async->prealloc_bufsz / in ni_cdio_cmdtest()
3617 if (cmd->chanlist && cmd->chanlist_len > 0) in ni_cdio_cmdtest()
3630 struct comedi_cmd *cmd = &s->async->cmd; in ni_cdo_inttrig()
3634 struct ni_private *devpriv = dev->private; in ni_cdo_inttrig()
3637 if (trig_num != cmd->start_arg) in ni_cdo_inttrig()
3638 return -EINVAL; in ni_cdo_inttrig()
3640 s->async->inttrig = NULL; in ni_cdo_inttrig()
3643 comedi_buf_read_alloc(s, s->async->prealloc_bufsz); in ni_cdo_inttrig()
3645 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in ni_cdo_inttrig()
3646 if (devpriv->cdo_mite_chan) { in ni_cdo_inttrig()
3647 mite_prep_dma(devpriv->cdo_mite_chan, 32, 32); in ni_cdo_inttrig()
3648 mite_dma_arm(devpriv->cdo_mite_chan); in ni_cdo_inttrig()
3650 dev_err(dev->class_dev, "BUG: no cdo mite channel?\n"); in ni_cdo_inttrig()
3651 retval = -EIO; in ni_cdo_inttrig()
3653 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in ni_cdo_inttrig()
3669 dev_err(dev->class_dev, "dma failed to fill cdo fifo!\n"); in ni_cdo_inttrig()
3670 s->cancel(dev, s); in ni_cdo_inttrig()
3671 return -EIO; in ni_cdo_inttrig()
3682 struct ni_private *devpriv = dev->private; in ni_cdio_cmd()
3683 const struct comedi_cmd *cmd = &s->async->cmd; in ni_cdio_cmd()
3696 CR_CHAN(cmd->scan_begin_arg), in ni_cdio_cmd()
3698 &devpriv->routing_tables)); in ni_cdio_cmd()
3699 if (cmd->scan_begin_arg & CR_INVERT) in ni_cdio_cmd()
3702 if (s->io_bits) { in ni_cdio_cmd()
3703 ni_writel(dev, s->state, NI_M_CDO_FIFO_DATA_REG); in ni_cdio_cmd()
3705 ni_writel(dev, s->io_bits, NI_M_CDO_MASK_ENA_REG); in ni_cdio_cmd()
3707 dev_err(dev->class_dev, in ni_cdio_cmd()
3709 return -EIO; in ni_cdio_cmd()
3715 ni_cmd_set_mite_transfer(devpriv->cdo_mite_ring, s, cmd, in ni_cdio_cmd()
3716 s->async->prealloc_bufsz / in ni_cdio_cmd()
3719 s->async->inttrig = ni_cdo_inttrig; in ni_cdio_cmd()
3742 struct ni_private *devpriv = dev->private; in handle_cdio_interrupt()
3744 struct comedi_subdevice *s = &dev->subdevices[NI_DIO_SUBDEV]; in handle_cdio_interrupt()
3747 spin_lock_irqsave(&devpriv->mite_channel_lock, flags); in handle_cdio_interrupt()
3748 if (devpriv->cdo_mite_chan) in handle_cdio_interrupt()
3749 mite_ack_linkc(devpriv->cdo_mite_chan, s, true); in handle_cdio_interrupt()
3750 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags); in handle_cdio_interrupt()
3757 s->async->events |= COMEDI_CB_OVERFLOW; in handle_cdio_interrupt()
3762 /* s->async->events |= COMEDI_CB_EOA; */ in handle_cdio_interrupt()
3773 struct ni_private *devpriv = dev->private; in ni_serial_hw_readwrite8()
3777 devpriv->dio_output &= ~NISTC_DIO_OUT_SERIAL_MASK; in ni_serial_hw_readwrite8()
3778 devpriv->dio_output |= NISTC_DIO_OUT_SERIAL(data_out); in ni_serial_hw_readwrite8()
3779 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG); in ni_serial_hw_readwrite8()
3783 err = -EBUSY; in ni_serial_hw_readwrite8()
3787 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_START; in ni_serial_hw_readwrite8()
3788 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG); in ni_serial_hw_readwrite8()
3789 devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_START; in ni_serial_hw_readwrite8()
3795 udelay((devpriv->serial_interval_ns + 999) / 1000); in ni_serial_hw_readwrite8()
3796 if (--count < 0) { in ni_serial_hw_readwrite8()
3797 dev_err(dev->class_dev, in ni_serial_hw_readwrite8()
3799 err = -ETIME; in ni_serial_hw_readwrite8()
3808 udelay((devpriv->serial_interval_ns + 999) / 1000); in ni_serial_hw_readwrite8()
3814 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG); in ni_serial_hw_readwrite8()
3824 struct ni_private *devpriv = dev->private; in ni_serial_sw_readwrite8()
3828 udelay((devpriv->serial_interval_ns + 999) / 1000); in ni_serial_sw_readwrite8()
3832 * Output current bit; note that we cannot touch s->state in ni_serial_sw_readwrite8()
3833 * because it is a per-subdevice field, and serial is in ni_serial_sw_readwrite8()
3836 devpriv->dio_output &= ~NISTC_DIO_SDOUT; in ni_serial_sw_readwrite8()
3838 devpriv->dio_output |= NISTC_DIO_SDOUT; in ni_serial_sw_readwrite8()
3839 ni_stc_writew(dev, devpriv->dio_output, NISTC_DIO_OUT_REG); in ni_serial_sw_readwrite8()
3845 devpriv->dio_control |= NISTC_DIO_SDCLK; in ni_serial_sw_readwrite8()
3846 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG); in ni_serial_sw_readwrite8()
3848 udelay((devpriv->serial_interval_ns + 999) / 2000); in ni_serial_sw_readwrite8()
3850 devpriv->dio_control &= ~NISTC_DIO_SDCLK; in ni_serial_sw_readwrite8()
3851 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG); in ni_serial_sw_readwrite8()
3853 udelay((devpriv->serial_interval_ns + 999) / 2000); in ni_serial_sw_readwrite8()
3871 struct ni_private *devpriv = dev->private; in ni_serial_insn_config()
3872 unsigned int clk_fout = devpriv->clock_and_fout; in ni_serial_insn_config()
3873 int err = insn->n; in ni_serial_insn_config()
3876 if (insn->n != 2) in ni_serial_insn_config()
3877 return -EINVAL; in ni_serial_insn_config()
3881 devpriv->serial_hw_mode = 1; in ni_serial_insn_config()
3882 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_ENA; in ni_serial_insn_config()
3885 devpriv->serial_hw_mode = 0; in ni_serial_insn_config()
3886 devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA | in ni_serial_insn_config()
3889 devpriv->serial_interval_ns = data[1]; in ni_serial_insn_config()
3895 devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE; in ni_serial_insn_config()
3899 devpriv->serial_interval_ns = data[1]; in ni_serial_insn_config()
3901 devpriv->dio_control &= ~NISTC_DIO_CTRL_HW_SER_TIMEBASE; in ni_serial_insn_config()
3905 devpriv->serial_interval_ns = data[1]; in ni_serial_insn_config()
3907 devpriv->dio_control |= NISTC_DIO_CTRL_HW_SER_TIMEBASE; in ni_serial_insn_config()
3917 devpriv->serial_interval_ns = data[1]; in ni_serial_insn_config()
3919 devpriv->dio_control &= ~(NISTC_DIO_CTRL_HW_SER_ENA | in ni_serial_insn_config()
3921 devpriv->serial_hw_mode = 0; in ni_serial_insn_config()
3923 devpriv->serial_interval_ns = data[1]; in ni_serial_insn_config()
3925 devpriv->clock_and_fout = clk_fout; in ni_serial_insn_config()
3927 ni_stc_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG); in ni_serial_insn_config()
3928 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG); in ni_serial_insn_config()
3933 if (devpriv->serial_interval_ns == 0) in ni_serial_insn_config()
3934 return -EINVAL; in ni_serial_insn_config()
3938 if (devpriv->serial_hw_mode) { in ni_serial_insn_config()
3941 } else if (devpriv->serial_interval_ns > 0) { in ni_serial_insn_config()
3945 dev_err(dev->class_dev, "serial disabled!\n"); in ni_serial_insn_config()
3946 return -EINVAL; in ni_serial_insn_config()
3951 return insn->n; in ni_serial_insn_config()
3955 return -EINVAL; in ni_serial_insn_config()
3963 for (i = 0; i < s->n_chan; i++) { in init_ao_67xx()
3987 [NITIO_G0_CNT_MODE] = { 0x1b0, 2 }, /* M-Series only */
3988 [NITIO_G1_CNT_MODE] = { 0x1b2, 2 }, /* M-Series only */
3989 [NITIO_G0_GATE2] = { 0x1b4, 2 }, /* M-Series only */
3990 [NITIO_G1_GATE2] = { 0x1b6, 2 }, /* M-Series only */
3995 [NITIO_G0_DMA_CFG] = { 0x1b8, 2 }, /* M-Series only */
3996 [NITIO_G1_DMA_CFG] = { 0x1ba, 2 }, /* M-Series only */
3997 [NITIO_G0_DMA_STATUS] = { 0x1b8, 2 }, /* M-Series only */
3998 [NITIO_G1_DMA_STATUS] = { 0x1ba, 2 }, /* M-Series only */
3999 [NITIO_G0_ABZ] = { 0x1c0, 2 }, /* M-Series only */
4000 [NITIO_G1_ABZ] = { 0x1c2, 2 }, /* M-Series only */
4017 dev_warn(dev->class_dev, "%s: unhandled register=0x%x\n", in ni_gpct_to_stc_register()
4022 return regmap->mio_reg; in ni_gpct_to_stc_register()
4028 struct comedi_device *dev = counter->counter_dev->dev; in ni_gpct_write_register()
4035 /* m-series only registers */ in ni_gpct_write_register()
4074 struct comedi_device *dev = counter->counter_dev->dev; in ni_gpct_read_register()
4081 /* m-series only registers */ in ni_gpct_read_register()
4104 struct ni_private *devpriv = dev->private; in ni_freq_out_insn_read()
4105 unsigned int val = NISTC_CLK_FOUT_TO_DIVIDER(devpriv->clock_and_fout); in ni_freq_out_insn_read()
4108 for (i = 0; i < insn->n; i++) in ni_freq_out_insn_read()
4111 return insn->n; in ni_freq_out_insn_read()
4119 struct ni_private *devpriv = dev->private; in ni_freq_out_insn_write()
4121 if (insn->n) { in ni_freq_out_insn_write()
4122 unsigned int val = data[insn->n - 1]; in ni_freq_out_insn_write()
4124 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_ENA; in ni_freq_out_insn_write()
4125 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG); in ni_freq_out_insn_write()
4126 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_DIVIDER_MASK; in ni_freq_out_insn_write()
4129 devpriv->clock_and_fout |= NISTC_CLK_FOUT_DIVIDER(val); in ni_freq_out_insn_write()
4131 devpriv->clock_and_fout |= NISTC_CLK_FOUT_ENA; in ni_freq_out_insn_write()
4132 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG); in ni_freq_out_insn_write()
4134 return insn->n; in ni_freq_out_insn_write()
4142 struct ni_private *devpriv = dev->private; in ni_freq_out_insn_config()
4148 devpriv->clock_and_fout &= ~NISTC_CLK_FOUT_TIMEBASE_SEL; in ni_freq_out_insn_config()
4151 devpriv->clock_and_fout |= NISTC_CLK_FOUT_TIMEBASE_SEL; in ni_freq_out_insn_config()
4154 return -EINVAL; in ni_freq_out_insn_config()
4156 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG); in ni_freq_out_insn_config()
4159 if (devpriv->clock_and_fout & NISTC_CLK_FOUT_TIMEBASE_SEL) { in ni_freq_out_insn_config()
4168 return -EINVAL; in ni_freq_out_insn_config()
4170 return insn->n; in ni_freq_out_insn_config()
4186 struct ni_private *devpriv = dev->private; in ni_get_pwm_config()
4188 data[1] = devpriv->pwm_up_count * devpriv->clock_ns; in ni_get_pwm_config()
4189 data[2] = devpriv->pwm_down_count * devpriv->clock_ns; in ni_get_pwm_config()
4198 struct ni_private *devpriv = dev->private; in ni_m_series_pwm_config()
4206 devpriv->clock_ns); in ni_m_series_pwm_config()
4209 up_count = data[2] / devpriv->clock_ns; in ni_m_series_pwm_config()
4213 DIV_ROUND_UP(data[2], devpriv->clock_ns); in ni_m_series_pwm_config()
4216 return -EINVAL; in ni_m_series_pwm_config()
4221 devpriv->clock_ns); in ni_m_series_pwm_config()
4224 down_count = data[4] / devpriv->clock_ns; in ni_m_series_pwm_config()
4228 DIV_ROUND_UP(data[4], devpriv->clock_ns); in ni_m_series_pwm_config()
4231 return -EINVAL; in ni_m_series_pwm_config()
4233 if (up_count * devpriv->clock_ns != data[2] || in ni_m_series_pwm_config()
4234 down_count * devpriv->clock_ns != data[4]) { in ni_m_series_pwm_config()
4235 data[2] = up_count * devpriv->clock_ns; in ni_m_series_pwm_config()
4236 data[4] = down_count * devpriv->clock_ns; in ni_m_series_pwm_config()
4237 return -EAGAIN; in ni_m_series_pwm_config()
4242 devpriv->pwm_up_count = up_count; in ni_m_series_pwm_config()
4243 devpriv->pwm_down_count = down_count; in ni_m_series_pwm_config()
4248 return -EINVAL; in ni_m_series_pwm_config()
4258 struct ni_private *devpriv = dev->private; in ni_6143_pwm_config()
4266 devpriv->clock_ns); in ni_6143_pwm_config()
4269 up_count = data[2] / devpriv->clock_ns; in ni_6143_pwm_config()
4273 DIV_ROUND_UP(data[2], devpriv->clock_ns); in ni_6143_pwm_config()
4276 return -EINVAL; in ni_6143_pwm_config()
4281 devpriv->clock_ns); in ni_6143_pwm_config()
4284 down_count = data[4] / devpriv->clock_ns; in ni_6143_pwm_config()
4288 DIV_ROUND_UP(data[4], devpriv->clock_ns); in ni_6143_pwm_config()
4291 return -EINVAL; in ni_6143_pwm_config()
4293 if (up_count * devpriv->clock_ns != data[2] || in ni_6143_pwm_config()
4294 down_count * devpriv->clock_ns != data[4]) { in ni_6143_pwm_config()
4295 data[2] = up_count * devpriv->clock_ns; in ni_6143_pwm_config()
4296 data[4] = down_count * devpriv->clock_ns; in ni_6143_pwm_config()
4297 return -EAGAIN; in ni_6143_pwm_config()
4300 devpriv->pwm_up_count = up_count; in ni_6143_pwm_config()
4302 devpriv->pwm_down_count = down_count; in ni_6143_pwm_config()
4307 return -EINVAL; in ni_6143_pwm_config()
4320 * 1-12, whereas we use channel numbers 0-11. The NI in pack_mb88341()
4321 * docs use 1-12, also, so be careful here. in pack_mb88341()
4378 const struct ni_board_struct *board = dev->board_ptr; in ni_write_caldac()
4379 struct ni_private *devpriv = dev->private; in ni_write_caldac()
4385 if (devpriv->caldacs[addr] == val) in ni_write_caldac()
4387 devpriv->caldacs[addr] = val; in ni_write_caldac()
4390 type = board->caldac[i]; in ni_write_caldac()
4398 addr -= caldacs[type].n_chans; in ni_write_caldac()
4405 for (bit = 1 << (bits - 1); bit; bit >>= 1) { in ni_write_caldac()
4422 if (insn->n) { in ni_calib_insn_write()
4424 ni_write_caldac(dev, CR_CHAN(insn->chanspec), in ni_calib_insn_write()
4425 data[insn->n - 1]); in ni_calib_insn_write()
4428 return insn->n; in ni_calib_insn_write()
4436 struct ni_private *devpriv = dev->private; in ni_calib_insn_read()
4439 for (i = 0; i < insn->n; i++) in ni_calib_insn_read()
4440 data[0] = devpriv->caldacs[CR_CHAN(insn->chanspec)]; in ni_calib_insn_read()
4442 return insn->n; in ni_calib_insn_read()
4447 const struct ni_board_struct *board = dev->board_ptr; in caldac_setup()
4448 struct ni_private *devpriv = dev->private; in caldac_setup()
4457 type = board->caldac[0]; in caldac_setup()
4462 type = board->caldac[i]; in caldac_setup()
4470 s->n_chan = n_chans; in caldac_setup()
4473 unsigned int *maxdata_list = devpriv->caldac_maxdata_list; in caldac_setup()
4476 dev_err(dev->class_dev, in caldac_setup()
4478 s->maxdata_list = maxdata_list; in caldac_setup()
4481 type = board->caldac[i]; in caldac_setup()
4484 (1 << caldacs[type].n_bits) - 1; in caldac_setup()
4489 for (chan = 0; chan < s->n_chan; chan++) in caldac_setup()
4490 ni_write_caldac(dev, i, s->maxdata_list[i] / 2); in caldac_setup()
4492 type = board->caldac[0]; in caldac_setup()
4493 s->maxdata = (1 << caldacs[type].n_bits) - 1; in caldac_setup()
4495 for (chan = 0; chan < s->n_chan; chan++) in caldac_setup()
4496 ni_write_caldac(dev, i, s->maxdata / 2); in caldac_setup()
4538 if (insn->n) { in ni_eeprom_insn_read()
4539 val = ni_read_eeprom(dev, CR_CHAN(insn->chanspec)); in ni_eeprom_insn_read()
4540 for (i = 0; i < insn->n; i++) in ni_eeprom_insn_read()
4543 return insn->n; in ni_eeprom_insn_read()
4551 struct ni_private *devpriv = dev->private; in ni_m_series_eeprom_insn_read()
4554 for (i = 0; i < insn->n; i++) in ni_m_series_eeprom_insn_read()
4555 data[i] = devpriv->eeprom_buffer[CR_CHAN(insn->chanspec)]; in ni_m_series_eeprom_insn_read()
4557 return insn->n; in ni_m_series_eeprom_insn_read()
4563 /* pre-m-series boards have fixed signals on pfi pins */ in ni_old_get_pfi_routing()
4586 dev_err(dev->class_dev, "bug, unhandled case in switch.\n"); in ni_old_get_pfi_routing()
4595 /* pre-m-series boards have fixed signals on pfi pins */ in ni_old_set_pfi_routing()
4597 return -EINVAL; in ni_old_set_pfi_routing()
4604 struct ni_private *devpriv = dev->private; in ni_m_series_get_pfi_routing()
4608 devpriv->pfi_output_select_reg[array_offset]); in ni_m_series_get_pfi_routing()
4614 struct ni_private *devpriv = dev->private; in ni_m_series_set_pfi_routing()
4616 unsigned short val = devpriv->pfi_output_select_reg[index]; in ni_m_series_set_pfi_routing()
4619 return -EINVAL; in ni_m_series_set_pfi_routing()
4624 devpriv->pfi_output_select_reg[index] = val; in ni_m_series_set_pfi_routing()
4632 struct ni_private *devpriv = dev->private; in ni_get_pfi_routing()
4636 chan -= NI_PFI(0); in ni_get_pfi_routing()
4638 return (devpriv->is_m_series) in ni_get_pfi_routing()
4647 struct ni_private *devpriv = dev->private; in ni_set_pfi_routing()
4651 chan -= NI_PFI(0); in ni_set_pfi_routing()
4653 return (devpriv->is_m_series) in ni_set_pfi_routing()
4662 struct ni_private *devpriv = dev->private; in ni_config_pfi_filter()
4665 if (!devpriv->is_m_series) in ni_config_pfi_filter()
4666 return -ENOTSUPP; in ni_config_pfi_filter()
4670 chan -= NI_PFI(0); in ni_config_pfi_filter()
4685 chan -= NI_PFI(0); in ni_set_pfi_direction()
4693 struct ni_private *devpriv = dev->private; in ni_get_pfi_direction()
4697 chan -= NI_PFI(0); in ni_get_pfi_direction()
4699 return devpriv->io_bidirection_pin_reg & (1 << chan) ? in ni_get_pfi_direction()
4710 if (insn->n < 1) in ni_pfi_insn_config()
4711 return -EINVAL; in ni_pfi_insn_config()
4713 chan = CR_CHAN(insn->chanspec); in ni_pfi_insn_config()
4731 return -EINVAL; in ni_pfi_insn_config()
4741 struct ni_private *devpriv = dev->private; in ni_pfi_insn_bits()
4743 if (!devpriv->is_m_series) in ni_pfi_insn_bits()
4744 return -ENOTSUPP; in ni_pfi_insn_bits()
4747 ni_writew(dev, s->state, NI_M_PFI_DO_REG); in ni_pfi_insn_bits()
4751 return insn->n; in ni_pfi_insn_bits()
4766 return -EIO; in cs5529_wait_for_idle()
4769 dev_err(dev->class_dev, "timeout\n"); in cs5529_wait_for_idle()
4770 return -ETIME; in cs5529_wait_for_idle()
4792 dev_err(dev->class_dev, in cs5529_command()
4793 "possible problem - never saw adc go busy?\n"); in cs5529_command()
4805 dev_err(dev->class_dev, in cs5529_do_conversion()
4806 "timeout or signal in %s()\n", __func__); in cs5529_do_conversion()
4807 return -ETIME; in cs5529_do_conversion()
4811 dev_err(dev->class_dev, in cs5529_do_conversion()
4813 return -EIO; in cs5529_do_conversion()
4816 dev_err(dev->class_dev, in cs5529_do_conversion()
4843 if (insn->chanspec & CR_ALT_SOURCE) in cs5529_ai_insn_read()
4846 channel_select = CR_CHAN(insn->chanspec); in cs5529_ai_insn_read()
4849 for (n = 0; n < insn->n; n++) { in cs5529_ai_insn_read()
4855 return insn->n; in cs5529_ai_insn_read()
4866 dev_err(dev->class_dev, in cs5529_config_write()
4867 "timeout or signal in %s\n", __func__); in cs5529_config_write()
4876 /* do self-calibration */ in init_cs5529()
4887 dev_err(dev->class_dev, in init_cs5529()
4888 "timeout or signal in %s\n", __func__); in init_cs5529()
4910 * m-series wants the phased-locked loop to output 80MHz, which is in ni_mseries_get_pll_parameters()
4920 if (abs(new_period_ps - target_picosec) < in ni_mseries_get_pll_parameters()
4921 abs(best_period_picosec - target_picosec)) { in ni_mseries_get_pll_parameters()
4929 return -EIO; in ni_mseries_get_pll_parameters()
4943 struct ni_private *devpriv = dev->private; in ni_mseries_set_pll_master_clock()
4961 dev_err(dev->class_dev, in ni_mseries_set_pll_master_clock()
4962 …"%s: you must specify an input clock frequency between %i and %i nanosec for the phased-lock loop\… in ni_mseries_set_pll_master_clock()
4964 return -EINVAL; in ni_mseries_set_pll_master_clock()
4966 devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK; in ni_mseries_set_pll_master_clock()
4967 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg, in ni_mseries_set_pll_master_clock()
4970 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_TIMEBASE1_PLL | in ni_mseries_set_pll_master_clock()
4972 devpriv->clock_and_fout2 &= ~NI_M_CLK_FOUT2_PLL_SRC_MASK; in ni_mseries_set_pll_master_clock()
4975 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_STAR; in ni_mseries_set_pll_master_clock()
4979 devpriv->clock_and_fout2 |= NI_M_CLK_FOUT2_PLL_SRC_PXI10; in ni_mseries_set_pll_master_clock()
4984 devpriv->clock_and_fout2 |= in ni_mseries_set_pll_master_clock()
4990 return -EINVAL; in ni_mseries_set_pll_master_clock()
4996 &devpriv->clock_ns); in ni_mseries_set_pll_master_clock()
4998 dev_err(dev->class_dev, in ni_mseries_set_pll_master_clock()
5003 ni_writew(dev, devpriv->clock_and_fout2, NI_M_CLK_FOUT2_REG); in ni_mseries_set_pll_master_clock()
5008 devpriv->clock_source = source; in ni_mseries_set_pll_master_clock()
5016 dev_err(dev->class_dev, in ni_mseries_set_pll_master_clock()
5019 return -ETIMEDOUT; in ni_mseries_set_pll_master_clock()
5027 struct ni_private *devpriv = dev->private; in ni_set_master_clock()
5030 devpriv->rtsi_trig_direction_reg &= ~NISTC_RTSI_TRIG_USE_CLK; in ni_set_master_clock()
5031 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg, in ni_set_master_clock()
5033 devpriv->clock_ns = TIMEBASE_1_NS; in ni_set_master_clock()
5034 if (devpriv->is_m_series) { in ni_set_master_clock()
5035 devpriv->clock_and_fout2 &= in ni_set_master_clock()
5038 ni_writew(dev, devpriv->clock_and_fout2, in ni_set_master_clock()
5042 devpriv->clock_source = source; in ni_set_master_clock()
5044 if (devpriv->is_m_series) { in ni_set_master_clock()
5049 devpriv->rtsi_trig_direction_reg |= in ni_set_master_clock()
5052 devpriv->rtsi_trig_direction_reg, in ni_set_master_clock()
5055 dev_err(dev->class_dev, in ni_set_master_clock()
5057 return -EINVAL; in ni_set_master_clock()
5059 devpriv->clock_ns = period_ns; in ni_set_master_clock()
5060 devpriv->clock_source = source; in ni_set_master_clock()
5062 return -EINVAL; in ni_set_master_clock()
5072 struct ni_private *devpriv = dev->private; in ni_valid_rtsi_output_source()
5074 if (chan >= NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) { in ni_valid_rtsi_output_source()
5079 dev_err(dev->class_dev, in ni_valid_rtsi_output_source()
5080 …"%s: invalid source for channel=%i, channel %i is always the RTSI clock for pre-m-series boards\n", in ni_valid_rtsi_output_source()
5101 return (devpriv->is_m_series) ? 1 : 0; in ni_valid_rtsi_output_source()
5110 struct ni_private *devpriv = dev->private; in ni_set_rtsi_routing()
5114 chan -= TRIGGER_LINE(0); in ni_set_rtsi_routing()
5117 return -EINVAL; in ni_set_rtsi_routing()
5119 devpriv->rtsi_trig_a_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan); in ni_set_rtsi_routing()
5120 devpriv->rtsi_trig_a_output_reg |= NISTC_RTSI_TRIG(chan, src); in ni_set_rtsi_routing()
5121 ni_stc_writew(dev, devpriv->rtsi_trig_a_output_reg, in ni_set_rtsi_routing()
5123 } else if (chan < NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) { in ni_set_rtsi_routing()
5124 devpriv->rtsi_trig_b_output_reg &= ~NISTC_RTSI_TRIG_MASK(chan); in ni_set_rtsi_routing()
5125 devpriv->rtsi_trig_b_output_reg |= NISTC_RTSI_TRIG(chan, src); in ni_set_rtsi_routing()
5126 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg, in ni_set_rtsi_routing()
5133 dev_err(dev->class_dev, "%s: unknown rtsi channel\n", __func__); in ni_set_rtsi_routing()
5134 return -EINVAL; in ni_set_rtsi_routing()
5142 struct ni_private *devpriv = dev->private; in ni_get_rtsi_routing()
5146 chan -= TRIGGER_LINE(0); in ni_get_rtsi_routing()
5150 devpriv->rtsi_trig_a_output_reg); in ni_get_rtsi_routing()
5151 } else if (chan < NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series)) { in ni_get_rtsi_routing()
5153 devpriv->rtsi_trig_b_output_reg); in ni_get_rtsi_routing()
5158 dev_err(dev->class_dev, "%s: unknown rtsi channel\n", __func__); in ni_get_rtsi_routing()
5159 return -EINVAL; in ni_get_rtsi_routing()
5165 struct ni_private *devpriv = dev->private; in ni_set_rtsi_direction()
5166 unsigned int max_chan = NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series); in ni_set_rtsi_direction()
5170 chan -= TRIGGER_LINE(0); in ni_set_rtsi_direction()
5174 devpriv->rtsi_trig_direction_reg |= in ni_set_rtsi_direction()
5175 NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series); in ni_set_rtsi_direction()
5177 devpriv->rtsi_trig_direction_reg |= in ni_set_rtsi_direction()
5182 devpriv->rtsi_trig_direction_reg &= in ni_set_rtsi_direction()
5183 ~NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series); in ni_set_rtsi_direction()
5185 devpriv->rtsi_trig_direction_reg &= in ni_set_rtsi_direction()
5189 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg, in ni_set_rtsi_direction()
5195 struct ni_private *devpriv = dev->private; in ni_get_rtsi_direction()
5196 unsigned int max_chan = NISTC_RTSI_TRIG_NUM_CHAN(devpriv->is_m_series); in ni_get_rtsi_direction()
5200 chan -= TRIGGER_LINE(0); in ni_get_rtsi_direction()
5203 return (devpriv->rtsi_trig_direction_reg & in ni_get_rtsi_direction()
5204 NISTC_RTSI_TRIG_DIR(chan, devpriv->is_m_series)) in ni_get_rtsi_direction()
5207 return (devpriv->rtsi_trig_direction_reg & in ni_get_rtsi_direction()
5211 return -EINVAL; in ni_get_rtsi_direction()
5219 struct ni_private *devpriv = dev->private; in ni_rtsi_insn_config()
5220 unsigned int chan = CR_CHAN(insn->chanspec); in ni_rtsi_insn_config()
5238 data[1] = devpriv->clock_source; in ni_rtsi_insn_config()
5239 data[2] = devpriv->clock_ns; in ni_rtsi_insn_config()
5252 return -EINVAL; in ni_rtsi_insn_config()
5264 return insn->n; in ni_rtsi_insn_bits()
5291 struct ni_private *devpriv = dev->private; in set_rgout0_reg()
5293 if (devpriv->is_m_series) { in set_rgout0_reg()
5294 devpriv->rtsi_trig_direction_reg &= in set_rgout0_reg()
5296 devpriv->rtsi_trig_direction_reg |= in set_rgout0_reg()
5299 ni_stc_writew(dev, devpriv->rtsi_trig_direction_reg, in set_rgout0_reg()
5302 devpriv->rtsi_trig_b_output_reg &= ~NISTC_RTSI_TRIGB_SUB_SEL1; in set_rgout0_reg()
5303 devpriv->rtsi_trig_b_output_reg |= in set_rgout0_reg()
5306 ni_stc_writew(dev, devpriv->rtsi_trig_b_output_reg, in set_rgout0_reg()
5313 struct ni_private *devpriv = dev->private; in get_rgout0_reg()
5316 if (devpriv->is_m_series) in get_rgout0_reg()
5317 reg = (devpriv->rtsi_trig_direction_reg & in get_rgout0_reg()
5321 reg = (devpriv->rtsi_trig_b_output_reg & in get_rgout0_reg()
5329 struct ni_private *devpriv = dev->private; in get_rgout0_src()
5332 return ni_find_route_source(reg, NI_RGOUT0, &devpriv->routing_tables); in get_rgout0_src()
5338 * @src: device-global signal name
5341 * Return: -EINVAL if the source is not valid to route to RGOUT0;
5342 * -EBUSY if the RGOUT0 is already used;
5347 struct ni_private *devpriv = dev->private; in incr_rgout0_src_use()
5349 &devpriv->routing_tables); in incr_rgout0_src_use()
5352 return -EINVAL; in incr_rgout0_src_use()
5354 if (devpriv->rgout0_usage > 0 && get_rgout0_reg(dev) != reg) in incr_rgout0_src_use()
5355 return -EBUSY; in incr_rgout0_src_use()
5357 ++devpriv->rgout0_usage; in incr_rgout0_src_use()
5366 * counter for the current src->RGOUT0 mapping.
5368 * Return: -EINVAL if the source is not already routed to RGOUT0 (or usage is
5373 struct ni_private *devpriv = dev->private; in decr_rgout0_src_use()
5375 &devpriv->routing_tables); in decr_rgout0_src_use()
5377 if (devpriv->rgout0_usage > 0 && get_rgout0_reg(dev) == reg) { in decr_rgout0_src_use()
5378 --devpriv->rgout0_usage; in decr_rgout0_src_use()
5379 if (!devpriv->rgout0_usage) in decr_rgout0_src_use()
5383 return -EINVAL; in decr_rgout0_src_use()
5394 struct ni_private *devpriv = dev->private; in set_ith_rtsi_brd_reg()
5395 int reg_i_sz = 3; /* value for e-series */ in set_ith_rtsi_brd_reg()
5399 if (devpriv->is_m_series) in set_ith_rtsi_brd_reg()
5405 devpriv->rtsi_shared_mux_reg &= ~(reg_i_mask << reg_i_shift); in set_ith_rtsi_brd_reg()
5407 devpriv->rtsi_shared_mux_reg |= (reg & reg_i_mask) << reg_i_shift; in set_ith_rtsi_brd_reg()
5409 ni_stc_writew(dev, devpriv->rtsi_shared_mux_reg, NISTC_RTSI_BOARD_REG); in set_ith_rtsi_brd_reg()
5414 struct ni_private *devpriv = dev->private; in get_ith_rtsi_brd_reg()
5415 int reg_i_sz = 3; /* value for e-series */ in get_ith_rtsi_brd_reg()
5419 if (devpriv->is_m_series) in get_ith_rtsi_brd_reg()
5424 return (devpriv->rtsi_shared_mux_reg >> reg_i_shift) & reg_i_mask; in get_ith_rtsi_brd_reg()
5429 struct ni_private *devpriv = dev->private; in get_rtsi_brd_src()
5434 brd_index = brd - NI_RTSI_BRD(0); in get_rtsi_brd_src()
5439 * brd : device-global name in get_rtsi_brd_src()
5445 return ni_find_route_source(reg, brd, &devpriv->routing_tables); in get_rtsi_brd_src()
5452 * Return: -EINVAL if the source is not valid to route to NI_RTSI_BRD(i);
5453 * -EBUSY if all NI_RTSI_BRD muxes are already used;
5458 struct ni_private *devpriv = dev->private; in incr_rtsi_brd_src_use()
5459 int first_available = -1; in incr_rtsi_brd_src_use()
5460 int err = -EINVAL; in incr_rtsi_brd_src_use()
5467 &devpriv->routing_tables); in incr_rtsi_brd_src_use()
5472 if (!devpriv->rtsi_shared_mux_usage[i]) { in incr_rtsi_brd_src_use()
5479 * final error to -EBUSY in case there are no muxes in incr_rtsi_brd_src_use()
5482 err = -EBUSY; in incr_rtsi_brd_src_use()
5487 * to provide the requested signal. Reuse it. in incr_rtsi_brd_src_use()
5501 ++devpriv->rtsi_shared_mux_usage[i]; in incr_rtsi_brd_src_use()
5510 * Return: -EINVAL if the source is not already routed to rtsi_brd(i) (or usage
5516 struct ni_private *devpriv = dev->private; in decr_rtsi_brd_src_use()
5518 &devpriv->routing_tables); in decr_rtsi_brd_src_use()
5519 const int i = rtsi_brd - NI_RTSI_BRD(0); in decr_rtsi_brd_src_use()
5521 if (devpriv->rtsi_shared_mux_usage[i] > 0 && in decr_rtsi_brd_src_use()
5523 --devpriv->rtsi_shared_mux_usage[i]; in decr_rtsi_brd_src_use()
5524 if (!devpriv->rtsi_shared_mux_usage[i]) in decr_rtsi_brd_src_use()
5529 return -EINVAL; in decr_rtsi_brd_src_use()
5534 struct ni_private *devpriv = dev->private; in ni_rtsi_init()
5537 /* Initialises the RTSI bus signal switch to a default state */ in ni_rtsi_init()
5541 * to have no effect, at least on pxi-6281, which always uses in ni_rtsi_init()
5544 devpriv->clock_and_fout2 = NI_M_CLK_FOUT2_RTSI_10MHZ; in ni_rtsi_init()
5547 dev_err(dev->class_dev, "ni_set_master_clock failed, bug?\n"); in ni_rtsi_init()
5558 * for e-series: in ni_rtsi_init()
5561 * for m-series: in ni_rtsi_init()
5564 devpriv->rtsi_shared_mux_reg = 0; in ni_rtsi_init()
5567 memset(devpriv->rtsi_shared_mux_usage, 0, in ni_rtsi_init()
5568 sizeof(devpriv->rtsi_shared_mux_usage)); in ni_rtsi_init()
5571 devpriv->rgout0_usage = 0; in ni_rtsi_init()
5579 struct ni_private *devpriv = dev->private; in ni_get_gout_routing()
5580 unsigned int reg = devpriv->an_trig_etc_reg; in ni_get_gout_routing()
5593 return -EINVAL; in ni_get_gout_routing()
5600 struct ni_private *devpriv = dev->private; in ni_disable_gout_routing()
5604 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_GPFO_0_ENA; in ni_disable_gout_routing()
5607 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_GPFO_1_ENA; in ni_disable_gout_routing()
5610 return -EINVAL; in ni_disable_gout_routing()
5613 ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG); in ni_disable_gout_routing()
5621 struct ni_private *devpriv = dev->private; in ni_set_gout_routing()
5626 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_GPFO_0_SEL(-1); in ni_set_gout_routing()
5628 devpriv->an_trig_etc_reg |= NISTC_ATRIG_ETC_GPFO_0_ENA in ni_set_gout_routing()
5633 devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_GPFO_1_SEL; in ni_set_gout_routing()
5636 devpriv->an_trig_etc_reg |= NISTC_ATRIG_ETC_GPFO_1_ENA | src; in ni_set_gout_routing()
5639 return -EINVAL; in ni_set_gout_routing()
5642 ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG); in ni_set_gout_routing()
5649 * as an output, this function returns -EINVAL as error.
5652 * -EINVAL if terminal is not configured for output.
5656 struct ni_private *devpriv = dev->private; in get_output_select_source()
5657 int reg = -1; in get_output_select_source()
5671 const int i = reg - NI_RTSI_OUTPUT_RTSI_BRD(0); in get_output_select_source()
5677 } else if (dest >= NI_CtrOut(0) && dest <= NI_CtrOut(-1)) { in get_output_select_source()
5682 dest -= NI_CtrOut(0); in get_output_select_source()
5685 return -EINVAL; in get_output_select_source()
5688 reg = ni_tio_get_routing(devpriv->counter_dev, dest); in get_output_select_source()
5690 dev_dbg(dev->class_dev, "%s: unhandled destination (%d) queried\n", in get_output_select_source()
5696 &devpriv->routing_tables); in get_output_select_source()
5697 return -EINVAL; in get_output_select_source()
5703 * Return: -1 if not connectible;
5710 struct ni_private *devpriv = dev->private; in test_route()
5712 &devpriv->routing_tables); in test_route()
5715 return -1; in test_route()
5725 struct ni_private *devpriv = dev->private; in connect_route()
5727 &devpriv->routing_tables); in connect_route()
5732 return -EINVAL; in connect_route()
5736 return -EALREADY; in connect_route()
5739 return -EBUSY; in connect_route()
5753 /* Attempt to allocate and route (src->brd) */ in connect_route()
5759 /* Now lookup the register value for (brd->dest) */ in connect_route()
5761 brd, dest, &devpriv->routing_tables); in connect_route()
5766 } else if (dest >= NI_CtrOut(0) && dest <= NI_CtrOut(-1)) { in connect_route()
5771 dest -= NI_CtrOut(0); in connect_route()
5774 return -EINVAL; in connect_route()
5776 return -EINVAL; in connect_route()
5782 ni_tio_set_routing(devpriv->counter_dev, dest, in connect_route()
5783 reg | (src & ~CR_CHAN(-1))); in connect_route()
5785 return -EINVAL; in connect_route()
5793 struct ni_private *devpriv = dev->private; in disconnect_route()
5795 &devpriv->routing_tables); in disconnect_route()
5799 return -EINVAL; in disconnect_route()
5802 return -EINVAL; in disconnect_route()
5819 &devpriv->routing_tables); in disconnect_route()
5829 reg = default_rtsi_routing[dest - TRIGGER_LINE(0)]; in disconnect_route()
5832 } else if (dest >= NI_CtrOut(0) && dest <= NI_CtrOut(-1)) { in disconnect_route()
5837 dest -= NI_CtrOut(0); in disconnect_route()
5840 return -EINVAL; in disconnect_route()
5843 ni_tio_unset_routing(devpriv->counter_dev, dest); in disconnect_route()
5845 return -EINVAL; in disconnect_route()
5867 return -EINVAL; in ni_global_insn_config()
5875 struct ni_gpct *counter = s->private; in ni_gpct_cmd()
5878 retval = ni_request_gpct_mite_channel(dev, counter->counter_index, in ni_gpct_cmd()
5881 dev_err(dev->class_dev, in ni_gpct_cmd()
5886 ni_e_series_enable_second_irq(dev, counter->counter_index, 1); in ni_gpct_cmd()
5893 struct ni_gpct *counter = s->private; in ni_gpct_cancel()
5897 ni_e_series_enable_second_irq(dev, counter->counter_index, 0); in ni_gpct_cancel()
5898 ni_release_gpct_mite_channel(dev, counter->counter_index); in ni_gpct_cancel()
5906 struct comedi_subdevice *s_ai = dev->read_subdev; in ni_E_interrupt()
5907 struct comedi_subdevice *s_ao = dev->write_subdev; in ni_E_interrupt()
5912 struct ni_private *devpriv = dev->private; in ni_E_interrupt()
5915 if (!dev->attached) in ni_E_interrupt()
5917 smp_mb(); /* make sure dev->attached is checked */ in ni_E_interrupt()
5920 spin_lock_irqsave(&dev->spinlock, flags); in ni_E_interrupt()
5924 if (devpriv->mite) { in ni_E_interrupt()
5927 spin_lock_irqsave(&devpriv->mite_channel_lock, flags_too); in ni_E_interrupt()
5928 if (s_ai && devpriv->ai_mite_chan) in ni_E_interrupt()
5929 mite_ack_linkc(devpriv->ai_mite_chan, s_ai, false); in ni_E_interrupt()
5930 if (s_ao && devpriv->ao_mite_chan) in ni_E_interrupt()
5931 mite_ack_linkc(devpriv->ao_mite_chan, s_ao, false); in ni_E_interrupt()
5932 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags_too); in ni_E_interrupt()
5952 if (devpriv->is_m_series) in ni_E_interrupt()
5956 spin_unlock_irqrestore(&dev->spinlock, flags); in ni_E_interrupt()
5966 return -ENOMEM; in ni_alloc_private()
5968 spin_lock_init(&devpriv->window_lock); in ni_alloc_private()
5969 spin_lock_init(&devpriv->soft_reg_copy_lock); in ni_alloc_private()
5970 spin_lock_init(&devpriv->mite_channel_lock); in ni_alloc_private()
5979 struct ni_private *devpriv = dev->private; in _ni_get_valid_routes()
5981 return ni_get_valid_routes(&devpriv->routing_tables, n_pairs, in _ni_get_valid_routes()
5988 const struct ni_board_struct *board = dev->board_ptr; in ni_E_init()
5989 struct ni_private *devpriv = dev->private; in ni_E_init()
5993 const char *dev_family = devpriv->is_m_series ? "ni_mseries" in ni_E_init()
5995 if (!IS_PCIMIO != !dev->mmio) { in ni_E_init()
5996 dev_err(dev->class_dev, in ni_E_init()
5998 KBUILD_MODNAME, board->name); in ni_E_init()
5999 return -ENXIO; in ni_E_init()
6002 /* prepare the device for globally-named routes. */ in ni_E_init()
6003 if (ni_assign_device_routes(dev_family, board->name, in ni_E_init()
6004 board->alt_route_name, in ni_E_init()
6005 &devpriv->routing_tables) < 0) { in ni_E_init()
6006 dev_warn(dev->class_dev, "%s: %s device has no signal routing table.\n", in ni_E_init()
6007 __func__, board->name); in ni_E_init()
6008 …dev_warn(dev->class_dev, "%s: High level NI signal names will not be available for this %s board.\… in ni_E_init()
6009 __func__, board->name); in ni_E_init()
6015 dev->insn_device_config = ni_global_insn_config; in ni_E_init()
6016 dev->get_valid_routes = _ni_get_valid_routes; in ni_E_init()
6019 if (board->n_aochan > MAX_N_AO_CHAN) { in ni_E_init()
6020 dev_err(dev->class_dev, "bug! n_aochan > MAX_N_AO_CHAN\n"); in ni_E_init()
6021 return -EINVAL; in ni_E_init()
6025 devpriv->clock_and_fout = NISTC_CLK_FOUT_SLOW_DIV2 | in ni_E_init()
6029 if (!devpriv->is_6xxx) { in ni_E_init()
6030 /* BEAM is this needed for PCI-6143 ?? */ in ni_E_init()
6031 devpriv->clock_and_fout |= (NISTC_CLK_FOUT_AI_OUT_DIV2 | in ni_E_init()
6034 ni_stc_writew(dev, devpriv->clock_and_fout, NISTC_CLK_FOUT_REG); in ni_E_init()
6041 s = &dev->subdevices[NI_AI_SUBDEV]; in ni_E_init()
6042 if (board->n_adchan) { in ni_E_init()
6043 s->type = COMEDI_SUBD_AI; in ni_E_init()
6044 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_DITHER; in ni_E_init()
6045 if (!devpriv->is_611x) in ni_E_init()
6046 s->subdev_flags |= SDF_GROUND | SDF_COMMON | SDF_OTHER; in ni_E_init()
6047 if (board->ai_maxdata > 0xffff) in ni_E_init()
6048 s->subdev_flags |= SDF_LSAMPL; in ni_E_init()
6049 if (devpriv->is_m_series) in ni_E_init()
6050 s->subdev_flags |= SDF_SOFT_CALIBRATED; in ni_E_init()
6051 s->n_chan = board->n_adchan; in ni_E_init()
6052 s->maxdata = board->ai_maxdata; in ni_E_init()
6053 s->range_table = ni_range_lkup[board->gainlkup]; in ni_E_init()
6054 s->insn_read = ni_ai_insn_read; in ni_E_init()
6055 s->insn_config = ni_ai_insn_config; in ni_E_init()
6056 if (dev->irq) { in ni_E_init()
6057 dev->read_subdev = s; in ni_E_init()
6058 s->subdev_flags |= SDF_CMD_READ; in ni_E_init()
6059 s->len_chanlist = 512; in ni_E_init()
6060 s->do_cmdtest = ni_ai_cmdtest; in ni_E_init()
6061 s->do_cmd = ni_ai_cmd; in ni_E_init()
6062 s->cancel = ni_ai_reset; in ni_E_init()
6063 s->poll = ni_ai_poll; in ni_E_init()
6064 s->munge = ni_ai_munge; in ni_E_init()
6066 if (devpriv->mite) in ni_E_init()
6067 s->async_dma_dir = DMA_FROM_DEVICE; in ni_E_init()
6073 s->type = COMEDI_SUBD_UNUSED; in ni_E_init()
6077 s = &dev->subdevices[NI_AO_SUBDEV]; in ni_E_init()
6078 if (board->n_aochan) { in ni_E_init()
6079 s->type = COMEDI_SUBD_AO; in ni_E_init()
6080 s->subdev_flags = SDF_WRITABLE | SDF_DEGLITCH | SDF_GROUND; in ni_E_init()
6081 if (devpriv->is_m_series) in ni_E_init()
6082 s->subdev_flags |= SDF_SOFT_CALIBRATED; in ni_E_init()
6083 s->n_chan = board->n_aochan; in ni_E_init()
6084 s->maxdata = board->ao_maxdata; in ni_E_init()
6085 s->range_table = board->ao_range_table; in ni_E_init()
6086 s->insn_config = ni_ao_insn_config; in ni_E_init()
6087 s->insn_write = ni_ao_insn_write; in ni_E_init()
6097 if (dev->irq && (board->ao_fifo_depth || devpriv->mite)) { in ni_E_init()
6098 dev->write_subdev = s; in ni_E_init()
6099 s->subdev_flags |= SDF_CMD_WRITE; in ni_E_init()
6100 s->len_chanlist = s->n_chan; in ni_E_init()
6101 s->do_cmdtest = ni_ao_cmdtest; in ni_E_init()
6102 s->do_cmd = ni_ao_cmd; in ni_E_init()
6103 s->cancel = ni_ao_reset; in ni_E_init()
6104 if (!devpriv->is_m_series) in ni_E_init()
6105 s->munge = ni_ao_munge; in ni_E_init()
6107 if (devpriv->mite) in ni_E_init()
6108 s->async_dma_dir = DMA_TO_DEVICE; in ni_E_init()
6111 if (devpriv->is_67xx) in ni_E_init()
6117 s->type = COMEDI_SUBD_UNUSED; in ni_E_init()
6121 s = &dev->subdevices[NI_DIO_SUBDEV]; in ni_E_init()
6122 s->type = COMEDI_SUBD_DIO; in ni_E_init()
6123 s->subdev_flags = SDF_WRITABLE | SDF_READABLE; in ni_E_init()
6124 s->n_chan = board->has_32dio_chan ? 32 : 8; in ni_E_init()
6125 s->maxdata = 1; in ni_E_init()
6126 s->range_table = &range_digital; in ni_E_init()
6127 if (devpriv->is_m_series) { in ni_E_init()
6129 s->subdev_flags |= SDF_LSAMPL; in ni_E_init()
6130 s->insn_bits = ni_m_series_dio_insn_bits; in ni_E_init()
6131 s->insn_config = ni_m_series_dio_insn_config; in ni_E_init()
6132 if (dev->irq) { in ni_E_init()
6133 s->subdev_flags |= SDF_CMD_WRITE /* | SDF_CMD_READ */; in ni_E_init()
6134 s->len_chanlist = s->n_chan; in ni_E_init()
6135 s->do_cmdtest = ni_cdio_cmdtest; in ni_E_init()
6136 s->do_cmd = ni_cdio_cmd; in ni_E_init()
6137 s->cancel = ni_cdio_cancel; in ni_E_init()
6139 /* M-series boards use DMA */ in ni_E_init()
6140 s->async_dma_dir = DMA_BIDIRECTIONAL; in ni_E_init()
6147 ni_writel(dev, s->io_bits, NI_M_DIO_DIR_REG); in ni_E_init()
6150 s->insn_bits = ni_dio_insn_bits; in ni_E_init()
6151 s->insn_config = ni_dio_insn_config; in ni_E_init()
6154 devpriv->dio_control = NISTC_DIO_CTRL_DIR(s->io_bits); in ni_E_init()
6155 ni_writew(dev, devpriv->dio_control, NISTC_DIO_CTRL_REG); in ni_E_init()
6159 s = &dev->subdevices[NI_8255_DIO_SUBDEV]; in ni_E_init()
6160 if (board->has_8255) { in ni_E_init()
6166 s->type = COMEDI_SUBD_UNUSED; in ni_E_init()
6170 s = &dev->subdevices[NI_UNUSED_SUBDEV]; in ni_E_init()
6171 s->type = COMEDI_SUBD_UNUSED; in ni_E_init()
6174 s = &dev->subdevices[NI_CALIBRATION_SUBDEV]; in ni_E_init()
6175 s->type = COMEDI_SUBD_CALIB; in ni_E_init()
6176 s->subdev_flags = SDF_INTERNAL; in ni_E_init()
6177 s->n_chan = 1; in ni_E_init()
6178 s->maxdata = 0; in ni_E_init()
6179 if (devpriv->is_m_series) { in ni_E_init()
6181 s->insn_config = ni_m_series_pwm_config; in ni_E_init()
6184 } else if (devpriv->is_6143) { in ni_E_init()
6186 s->insn_config = ni_6143_pwm_config; in ni_E_init()
6188 s->subdev_flags |= SDF_WRITABLE; in ni_E_init()
6189 s->insn_read = ni_calib_insn_read; in ni_E_init()
6190 s->insn_write = ni_calib_insn_write; in ni_E_init()
6197 s = &dev->subdevices[NI_EEPROM_SUBDEV]; in ni_E_init()
6198 s->type = COMEDI_SUBD_MEMORY; in ni_E_init()
6199 s->subdev_flags = SDF_READABLE | SDF_INTERNAL; in ni_E_init()
6200 s->maxdata = 0xff; in ni_E_init()
6201 if (devpriv->is_m_series) { in ni_E_init()
6202 s->n_chan = M_SERIES_EEPROM_SIZE; in ni_E_init()
6203 s->insn_read = ni_m_series_eeprom_insn_read; in ni_E_init()
6205 s->n_chan = 512; in ni_E_init()
6206 s->insn_read = ni_eeprom_insn_read; in ni_E_init()
6210 s = &dev->subdevices[NI_PFI_DIO_SUBDEV]; in ni_E_init()
6211 s->type = COMEDI_SUBD_DIO; in ni_E_init()
6212 s->maxdata = 1; in ni_E_init()
6213 if (devpriv->is_m_series) { in ni_E_init()
6214 s->n_chan = 16; in ni_E_init()
6215 s->insn_bits = ni_pfi_insn_bits; in ni_E_init()
6216 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; in ni_E_init()
6218 ni_writew(dev, s->state, NI_M_PFI_DO_REG); in ni_E_init()
6220 ni_writew(dev, devpriv->pfi_output_select_reg[i], in ni_E_init()
6224 s->n_chan = 10; in ni_E_init()
6225 s->subdev_flags = SDF_INTERNAL; in ni_E_init()
6227 s->insn_config = ni_pfi_insn_config; in ni_E_init()
6232 s = &dev->subdevices[NI_CS5529_CALIBRATION_SUBDEV]; in ni_E_init()
6233 if (devpriv->is_67xx) { in ni_E_init()
6234 s->type = COMEDI_SUBD_AI; in ni_E_init()
6235 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_INTERNAL; in ni_E_init()
6237 s->n_chan = board->n_aochan; in ni_E_init()
6238 s->maxdata = BIT(16) - 1; in ni_E_init()
6239 s->range_table = &range_unknown; /* XXX */ in ni_E_init()
6240 s->insn_read = cs5529_ai_insn_read; in ni_E_init()
6241 s->insn_config = NULL; in ni_E_init()
6244 s->type = COMEDI_SUBD_UNUSED; in ni_E_init()
6248 s = &dev->subdevices[NI_SERIAL_SUBDEV]; in ni_E_init()
6249 s->type = COMEDI_SUBD_SERIAL; in ni_E_init()
6250 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; in ni_E_init()
6251 s->n_chan = 1; in ni_E_init()
6252 s->maxdata = 0xff; in ni_E_init()
6253 s->insn_config = ni_serial_insn_config; in ni_E_init()
6254 devpriv->serial_interval_ns = 0; in ni_E_init()
6255 devpriv->serial_hw_mode = 0; in ni_E_init()
6258 s = &dev->subdevices[NI_RTSI_SUBDEV]; in ni_E_init()
6259 s->type = COMEDI_SUBD_DIO; in ni_E_init()
6260 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; in ni_E_init()
6261 s->n_chan = 8; in ni_E_init()
6262 s->maxdata = 1; in ni_E_init()
6263 s->insn_bits = ni_rtsi_insn_bits; in ni_E_init()
6264 s->insn_config = ni_rtsi_insn_config; in ni_E_init()
6268 devpriv->counter_dev = ni_gpct_device_construct(dev, in ni_E_init()
6271 (devpriv->is_m_series) in ni_E_init()
6276 &devpriv->routing_tables); in ni_E_init()
6277 if (!devpriv->counter_dev) in ni_E_init()
6278 return -ENOMEM; in ni_E_init()
6282 struct ni_gpct *gpct = &devpriv->counter_dev->counters[i]; in ni_E_init()
6287 s = &dev->subdevices[NI_GPCT_SUBDEV(i)]; in ni_E_init()
6288 s->type = COMEDI_SUBD_COUNTER; in ni_E_init()
6289 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL; in ni_E_init()
6290 s->n_chan = 3; in ni_E_init()
6291 s->maxdata = (devpriv->is_m_series) ? 0xffffffff in ni_E_init()
6293 s->insn_read = ni_tio_insn_read; in ni_E_init()
6294 s->insn_write = ni_tio_insn_write; in ni_E_init()
6295 s->insn_config = ni_tio_insn_config; in ni_E_init()
6297 if (dev->irq && devpriv->mite) { in ni_E_init()
6298 s->subdev_flags |= SDF_CMD_READ /* | SDF_CMD_WRITE */; in ni_E_init()
6299 s->len_chanlist = 1; in ni_E_init()
6300 s->do_cmdtest = ni_tio_cmdtest; in ni_E_init()
6301 s->do_cmd = ni_gpct_cmd; in ni_E_init()
6302 s->cancel = ni_gpct_cancel; in ni_E_init()
6304 s->async_dma_dir = DMA_BIDIRECTIONAL; in ni_E_init()
6307 s->private = gpct; in ni_E_init()
6315 s = &dev->subdevices[NI_FREQ_OUT_SUBDEV]; in ni_E_init()
6316 s->type = COMEDI_SUBD_COUNTER; in ni_E_init()
6317 s->subdev_flags = SDF_READABLE | SDF_WRITABLE; in ni_E_init()
6318 s->n_chan = 1; in ni_E_init()
6319 s->maxdata = 0xf; in ni_E_init()
6320 s->insn_read = ni_freq_out_insn_read; in ni_E_init()
6321 s->insn_write = ni_freq_out_insn_write; in ni_E_init()
6322 s->insn_config = ni_freq_out_insn_config; in ni_E_init()
6324 if (dev->irq) { in ni_E_init()
6336 ni_writeb(dev, devpriv->ai_ao_select_reg, NI_E_DMA_AI_AO_SEL_REG); in ni_E_init()
6337 ni_writeb(dev, devpriv->g0_g1_select_reg, NI_E_DMA_G0_G1_SEL_REG); in ni_E_init()
6339 if (devpriv->is_6xxx) { in ni_E_init()
6341 } else if (devpriv->is_m_series) { in ni_E_init()
6344 for (channel = 0; channel < board->n_aochan; ++channel) { in ni_E_init()
6358 struct ni_private *devpriv = dev->private; in mio_common_detach()
6361 ni_gpct_device_destroy(devpriv->counter_dev); in mio_common_detach()