Lines Matching +full:trigger +full:- +full:value

1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * Copyright 2012-2013 Freescale Semiconductor, Inc.
58 	/* set the max load value and start the clock source counter */  in pit_clocksource_init()
64 	return clocksource_mmio_init(clksrc_base + PITCVAL, "vf-pit", rate,  in pit_clocksource_init()
72 	 * set a new value to PITLDVAL register will not restart the timer,  in pit_set_next_event()
74 	 * value, the timer must be disabled and enabled again.  in pit_set_next_event()
79 	__raw_writel(delta - 1, clkevt_base + PITLDVAL);  in pit_set_next_event()
105 	 * and reload the counter value from PITLDVAL when PITCVAL reach zero,  in pit_timer_interrupt()
112 	evt->event_handler(evt);  in pit_timer_interrupt()
137 	 * The value for the LDVAL register trigger is calculated as:  in pit_clockevent_init()
138 	 * LDVAL trigger = (period / clock period) - 1  in pit_clockevent_init()
139 	 * The pit is a 32-bit down count timer, when the counter value  in pit_clockevent_init()
141 	 * LDVAL trigger value is 1. And then the min_delta is  in pit_clockevent_init()
142 	 * minimal LDVAL trigger value + 1, and the max_delta is full 32-bit.  in pit_clockevent_init()
159 		return -ENXIO;  in pit_timer_init()
163 	 * PIT0 and PIT1 can be chained to build a 64-bit timer,  in pit_timer_init()
172 		return -EINVAL;  in pit_timer_init()
194 TIMER_OF_DECLARE(vf610, "fsl,vf610-pit", pit_timer_init);