Lines Matching +full:tegra186 +full:- +full:timer
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2019-2025 NVIDIA Corporation. All rights reserved.
25 /* timer registers */
100 writel_relaxed(value, tmr->regs + offset); in tmr_writel()
105 writel_relaxed(value, wdt->regs + offset); in wdt_writel()
110 return readl_relaxed(wdt->regs + offset); in wdt_readl()
119 tmr = devm_kzalloc(tegra->dev, sizeof(*tmr), GFP_KERNEL); in tegra186_tmr_create()
121 return ERR_PTR(-ENOMEM); in tegra186_tmr_create()
123 tmr->parent = tegra; in tegra186_tmr_create()
124 tmr->regs = tegra->regs + offset; in tegra186_tmr_create()
125 tmr->index = index; in tegra186_tmr_create()
126 tmr->hwirq = 0; in tegra186_tmr_create()
133 .identity = "NVIDIA Tegra186 WDT",
142 /* disable timer */ in tegra186_wdt_disable()
143 tmr_writel(wdt->tmr, 0, TMRCR); in tegra186_wdt_disable()
148 struct tegra186_timer *tegra = wdt->tmr->parent; in tegra186_wdt_enable()
152 value = TKEIE_WDT_MASK(wdt->index, 1); in tegra186_wdt_enable()
153 writel(value, tegra->regs + TKEIE(wdt->tmr->hwirq)); in tegra186_wdt_enable()
156 tmr_writel(wdt->tmr, TMRSR_INTR_CLR, TMRSR); in tegra186_wdt_enable()
159 tmr_writel(wdt->tmr, TMRCSSR_SRC_USEC, TMRCSSR); in tegra186_wdt_enable()
161 /* configure timer (system reset happens on the fifth expiration) */ in tegra186_wdt_enable()
162 value = TMRCR_PTV(wdt->base.timeout * (USEC_PER_SEC / 5)) | in tegra186_wdt_enable()
164 tmr_writel(wdt->tmr, value, TMRCR); in tegra186_wdt_enable()
166 if (!wdt->locked) { in tegra186_wdt_enable()
169 /* select the proper timer source */ in tegra186_wdt_enable()
171 value |= WDTCR_TIMER_SOURCE(wdt->tmr->index); in tegra186_wdt_enable()
173 /* single timer period since that's already configured */ in tegra186_wdt_enable()
219 if (watchdog_active(&wdt->base)) in tegra186_wdt_set_timeout()
222 wdt->base.timeout = timeout; in tegra186_wdt_set_timeout()
224 if (watchdog_active(&wdt->base)) in tegra186_wdt_set_timeout()
236 if (!watchdog_active(&wdt->base)) { in tegra186_wdt_get_timeleft()
237 /* return zero if the watchdog timer is not activated. */ in tegra186_wdt_get_timeleft()
243 * watchdog timer and so when the watchdog timer is configured, in tegra186_wdt_get_timeleft()
256 val = readl_relaxed(wdt->regs + WDTSR); in tegra186_wdt_get_timeleft()
262 val = readl_relaxed(wdt->tmr->regs + TMRSR); in tegra186_wdt_get_timeleft()
269 * Note: Since wdt->base.timeout is bound to 255, the maximum in tegra186_wdt_get_timeleft()
274 * TMRSR_PCV is a 29-bit field. in tegra186_wdt_get_timeleft()
277 * timeleft can therefore not overflow, and 64-bit calculations in tegra186_wdt_get_timeleft()
280 timeleft += (wdt->base.timeout * (USEC_PER_SEC / 5)) * (4 - expiration); in tegra186_wdt_get_timeleft()
308 offset += tegra->soc->num_timers * 0x10000 + index * 0x10000; in tegra186_wdt_create()
310 wdt = devm_kzalloc(tegra->dev, sizeof(*wdt), GFP_KERNEL); in tegra186_wdt_create()
312 return ERR_PTR(-ENOMEM); in tegra186_wdt_create()
314 wdt->regs = tegra->regs + offset; in tegra186_wdt_create()
315 wdt->index = index; in tegra186_wdt_create()
321 wdt->locked = true; in tegra186_wdt_create()
325 wdt->tmr = tegra186_tmr_create(tegra, source); in tegra186_wdt_create()
326 if (IS_ERR(wdt->tmr)) in tegra186_wdt_create()
327 return ERR_CAST(wdt->tmr); in tegra186_wdt_create()
329 wdt->base.info = &tegra186_wdt_info; in tegra186_wdt_create()
330 wdt->base.ops = &tegra186_wdt_ops; in tegra186_wdt_create()
331 wdt->base.min_timeout = 1; in tegra186_wdt_create()
332 wdt->base.max_timeout = 255; in tegra186_wdt_create()
333 wdt->base.parent = tegra->dev; in tegra186_wdt_create()
335 err = watchdog_init_timeout(&wdt->base, 5, tegra->dev); in tegra186_wdt_create()
339 err = devm_watchdog_register_device(tegra->dev, &wdt->base); in tegra186_wdt_create()
352 hi = readl_relaxed(tegra->regs + TKETSC1); in tegra186_timer_tsc_read()
355 * The 56-bit value of the TSC is spread across two registers that are in tegra186_timer_tsc_read()
363 lo = readl_relaxed(tegra->regs + TKETSC0); in tegra186_timer_tsc_read()
364 hi = readl_relaxed(tegra->regs + TKETSC1); in tegra186_timer_tsc_read()
372 tegra->tsc.name = "tsc"; in tegra186_timer_tsc_init()
373 tegra->tsc.rating = 300; in tegra186_timer_tsc_init()
374 tegra->tsc.read = tegra186_timer_tsc_read; in tegra186_timer_tsc_init()
375 tegra->tsc.mask = CLOCKSOURCE_MASK(56); in tegra186_timer_tsc_init()
376 tegra->tsc.flags = CLOCK_SOURCE_IS_CONTINUOUS; in tegra186_timer_tsc_init()
377 tegra->tsc.owner = THIS_MODULE; in tegra186_timer_tsc_init()
379 return clocksource_register_hz(&tegra->tsc, 31250000); in tegra186_timer_tsc_init()
387 return readl_relaxed(tegra->regs + TKEOSC); in tegra186_timer_osc_read()
392 tegra->osc.name = "osc"; in tegra186_timer_osc_init()
393 tegra->osc.rating = 300; in tegra186_timer_osc_init()
394 tegra->osc.read = tegra186_timer_osc_read; in tegra186_timer_osc_init()
395 tegra->osc.mask = CLOCKSOURCE_MASK(32); in tegra186_timer_osc_init()
396 tegra->osc.flags = CLOCK_SOURCE_IS_CONTINUOUS; in tegra186_timer_osc_init()
397 tegra->osc.owner = THIS_MODULE; in tegra186_timer_osc_init()
399 return clocksource_register_hz(&tegra->osc, 38400000); in tegra186_timer_osc_init()
407 return readl_relaxed(tegra->regs + TKEUSEC); in tegra186_timer_usec_read()
412 tegra->usec.name = "usec"; in tegra186_timer_usec_init()
413 tegra->usec.rating = 300; in tegra186_timer_usec_init()
414 tegra->usec.read = tegra186_timer_usec_read; in tegra186_timer_usec_init()
415 tegra->usec.mask = CLOCKSOURCE_MASK(32); in tegra186_timer_usec_init()
416 tegra->usec.flags = CLOCK_SOURCE_IS_CONTINUOUS; in tegra186_timer_usec_init()
417 tegra->usec.owner = THIS_MODULE; in tegra186_timer_usec_init()
419 return clocksource_register_hz(&tegra->usec, USEC_PER_SEC); in tegra186_timer_usec_init()
424 struct device *dev = &pdev->dev; in tegra186_timer_probe()
430 return -ENOMEM; in tegra186_timer_probe()
432 tegra->soc = of_device_get_match_data(dev); in tegra186_timer_probe()
434 tegra->dev = dev; in tegra186_timer_probe()
436 tegra->regs = devm_platform_ioremap_resource(pdev, 0); in tegra186_timer_probe()
437 if (IS_ERR(tegra->regs)) in tegra186_timer_probe()
438 return PTR_ERR(tegra->regs); in tegra186_timer_probe()
444 /* create a watchdog using a preconfigured timer */ in tegra186_timer_probe()
445 tegra->wdt = tegra186_wdt_create(tegra, 0); in tegra186_timer_probe()
446 if (IS_ERR(tegra->wdt)) { in tegra186_timer_probe()
447 err = PTR_ERR(tegra->wdt); in tegra186_timer_probe()
473 clocksource_unregister(&tegra->osc); in tegra186_timer_probe()
475 clocksource_unregister(&tegra->tsc); in tegra186_timer_probe()
483 clocksource_unregister(&tegra->usec); in tegra186_timer_remove()
484 clocksource_unregister(&tegra->osc); in tegra186_timer_remove()
485 clocksource_unregister(&tegra->tsc); in tegra186_timer_remove()
492 if (watchdog_active(&tegra->wdt->base)) in tegra186_timer_suspend()
493 tegra186_wdt_disable(tegra->wdt); in tegra186_timer_suspend()
502 if (watchdog_active(&tegra->wdt->base)) in tegra186_timer_resume()
503 tegra186_wdt_enable(tegra->wdt); in tegra186_timer_resume()
522 { .compatible = "nvidia,tegra186-timer", .data = &tegra186_timer },
523 { .compatible = "nvidia,tegra234-timer", .data = &tegra234_timer },
530 .name = "tegra186-timer",
540 MODULE_DESCRIPTION("NVIDIA Tegra186 timers driver");