Lines Matching defs:ce
68 static void sun5i_clkevt_sync(struct sun5i_timer *ce)
70 u32 offset = ce->quirks->from_ctl_base_offset;
71 u32 old = readl(ce->base + TIMER_CNTVAL_LO_REG(1, offset));
73 while ((old - readl(ce->base + TIMER_CNTVAL_LO_REG(1, offset))) <
78 static void sun5i_clkevt_time_stop(struct sun5i_timer *ce, u8 timer)
80 u32 offset = ce->quirks->from_ctl_base_offset;
81 u32 val = readl(ce->base + TIMER_CTL_REG(timer, offset));
84 ce->base + TIMER_CTL_REG(timer, offset));
86 sun5i_clkevt_sync(ce);
89 static void sun5i_clkevt_time_setup(struct sun5i_timer *ce, u8 timer, u32 delay)
91 u32 offset = ce->quirks->from_ctl_base_offset;
93 writel(delay, ce->base + TIMER_INTVAL_LO_REG(timer, offset));
96 static void sun5i_clkevt_time_start(struct sun5i_timer *ce, u8 timer, bool periodic)
98 u32 offset = ce->quirks->from_ctl_base_offset;
99 u32 val = readl(ce->base + TIMER_CTL_REG(timer, offset));
107 ce->base + TIMER_CTL_REG(timer, offset));
112 struct sun5i_timer *ce = clkevt_to_sun5i_timer(clkevt);
114 sun5i_clkevt_time_stop(ce, 0);
120 struct sun5i_timer *ce = clkevt_to_sun5i_timer(clkevt);
122 sun5i_clkevt_time_stop(ce, 0);
123 sun5i_clkevt_time_start(ce, 0, false);
129 struct sun5i_timer *ce = clkevt_to_sun5i_timer(clkevt);
131 sun5i_clkevt_time_stop(ce, 0);
132 sun5i_clkevt_time_setup(ce, 0, ce->ticks_per_jiffy);
133 sun5i_clkevt_time_start(ce, 0, true);
140 struct sun5i_timer *ce = clkevt_to_sun5i_timer(clkevt);
142 sun5i_clkevt_time_stop(ce, 0);
143 sun5i_clkevt_time_setup(ce, 0, evt - TIMER_SYNC_TICKS);
144 sun5i_clkevt_time_start(ce, 0, false);
151 struct sun5i_timer *ce = dev_id;
153 writel(0x1, ce->base + TIMER_IRQ_ST_REG);
154 ce->clkevt.event_handler(&ce->clkevt);
223 struct sun5i_timer *ce = platform_get_drvdata(pdev);
224 void __iomem *base = ce->base;
228 ce->clkevt.name = dev->of_node->name;
229 ce->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
230 ce->clkevt.set_next_event = sun5i_clkevt_next_event;
231 ce->clkevt.set_state_shutdown = sun5i_clkevt_shutdown;
232 ce->clkevt.set_state_periodic = sun5i_clkevt_set_periodic;
233 ce->clkevt.set_state_oneshot = sun5i_clkevt_set_oneshot;
234 ce->clkevt.tick_resume = sun5i_clkevt_shutdown;
235 ce->clkevt.rating = 340;
236 ce->clkevt.irq = irq;
237 ce->clkevt.cpumask = cpu_possible_mask;
238 ce->clkevt.owner = THIS_MODULE;
244 clockevents_config_and_register(&ce->clkevt, rate,
249 "sun5i_timer0", ce);