37 static u32 mtk_cpux_readl(u32 reg_idx, struct timer_of *to)  in mtk_cpux_readl()  argument
39 	writel(reg_idx, timer_of_base(to) + CPUX_IDX_REG);  in mtk_cpux_readl()
40 	return readl(timer_of_base(to) + CPUX_CON_REG);  in mtk_cpux_readl()
43 static void mtk_cpux_writel(u32 val, u32 reg_idx, struct timer_of *to)  in mtk_cpux_writel()  argument
45 	writel(reg_idx, timer_of_base(to) + CPUX_IDX_REG);  in mtk_cpux_writel()
46 	writel(val, timer_of_base(to) + CPUX_CON_REG);  in mtk_cpux_writel()
49 static void mtk_cpux_set_irq(struct timer_of *to, bool enable)  in mtk_cpux_set_irq()  argument
54 	val = mtk_cpux_readl(CPUX_IDX_GLOBAL_IRQ, to);  in mtk_cpux_set_irq()
61 	mtk_cpux_writel(val, CPUX_IDX_GLOBAL_IRQ, to);  in mtk_cpux_set_irq()
83 static struct timer_of to = {  variable
106 	ret = timer_of_init(node, &to);  in mtk_cpux_init()
121 	freq = timer_of_rate(&to);  in mtk_cpux_init()
126 	val = mtk_cpux_readl(CPUX_IDX_GLOBAL_CTRL, &to);  in mtk_cpux_init()
129 	mtk_cpux_writel(val, CPUX_IDX_GLOBAL_CTRL, &to);  in mtk_cpux_init()
132 	val = mtk_cpux_readl(CPUX_IDX_GLOBAL_CTRL, &to);  in mtk_cpux_init()
133 	mtk_cpux_writel(val | CPUX_ENABLE, CPUX_IDX_GLOBAL_CTRL, &to);  in mtk_cpux_init()
135 	clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),  in mtk_cpux_init()