Lines Matching +full:local +full:- +full:timers
1 // SPDX-License-Identifier: GPL-2.0
6 * Based on a rewrite of arch/arm/mach-gemini/timer.c:
7 * Copyright (C) 2001-2006 Storlink, Corp.
8 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
46 * Control register (TMC30) bit fields for fttmr010/gemini/moxart timers.
62 * Control register (TMC30) bit fields for aspeed ast2400/ast2500 timers.
63 * The aspeed timers move bits around in the control register and lacks
78 * timers.
79 * The registers don't exist and they are not needed on aspeed timers
81 * - aspeed timer overflow interrupt is controlled by bits in Control
83 * - aspeed timers always generate interrupt when either one of the
112 * A local singleton used by sched_clock and delay timer reads, which are
124 return readl(local_fttmr->base + TIMER2_COUNT); in fttmr010_read_current_timer_up()
129 return ~readl(local_fttmr->base + TIMER2_COUNT); in fttmr010_read_current_timer_down()
149 fttmr010->timer_shutdown(evt); in fttmr010_timer_set_next_event()
151 if (fttmr010->is_aspeed) { in fttmr010_timer_set_next_event()
154 * into TIMER1_COUNT register when the timer is re-enabled. in fttmr010_timer_set_next_event()
156 writel(cycles, fttmr010->base + TIMER1_LOAD); in fttmr010_timer_set_next_event()
159 cr = readl(fttmr010->base + TIMER1_COUNT); in fttmr010_timer_set_next_event()
160 writel(cr + cycles, fttmr010->base + TIMER1_MATCH1); in fttmr010_timer_set_next_event()
164 cr = readl(fttmr010->base + TIMER_CR); in fttmr010_timer_set_next_event()
165 cr |= fttmr010->t1_enable_val; in fttmr010_timer_set_next_event()
166 writel(cr, fttmr010->base + TIMER_CR); in fttmr010_timer_set_next_event()
176 writel(fttmr010->t1_enable_val, fttmr010->base + AST2600_TIMER_CR_CLR); in ast2600_timer_shutdown()
187 cr = readl(fttmr010->base + TIMER_CR); in fttmr010_timer_shutdown()
188 cr &= ~fttmr010->t1_enable_val; in fttmr010_timer_shutdown()
189 writel(cr, fttmr010->base + TIMER_CR); in fttmr010_timer_shutdown()
200 fttmr010->timer_shutdown(evt); in fttmr010_timer_set_oneshot()
203 writel(0, fttmr010->base + TIMER1_COUNT); in fttmr010_timer_set_oneshot()
204 if (fttmr010->is_aspeed) { in fttmr010_timer_set_oneshot()
205 writel(~0, fttmr010->base + TIMER1_LOAD); in fttmr010_timer_set_oneshot()
207 writel(0, fttmr010->base + TIMER1_LOAD); in fttmr010_timer_set_oneshot()
210 cr = readl(fttmr010->base + TIMER_INTR_MASK); in fttmr010_timer_set_oneshot()
213 writel(cr, fttmr010->base + TIMER_INTR_MASK); in fttmr010_timer_set_oneshot()
222 u32 period = DIV_ROUND_CLOSEST(fttmr010->tick_rate, HZ); in fttmr010_timer_set_periodic()
226 fttmr010->timer_shutdown(evt); in fttmr010_timer_set_periodic()
229 if (fttmr010->is_aspeed) { in fttmr010_timer_set_periodic()
230 writel(period, fttmr010->base + TIMER1_LOAD); in fttmr010_timer_set_periodic()
232 cr = 0xffffffff - (period - 1); in fttmr010_timer_set_periodic()
233 writel(cr, fttmr010->base + TIMER1_COUNT); in fttmr010_timer_set_periodic()
234 writel(cr, fttmr010->base + TIMER1_LOAD); in fttmr010_timer_set_periodic()
237 cr = readl(fttmr010->base + TIMER_INTR_MASK); in fttmr010_timer_set_periodic()
240 writel(cr, fttmr010->base + TIMER_INTR_MASK); in fttmr010_timer_set_periodic()
244 cr = readl(fttmr010->base + TIMER_CR); in fttmr010_timer_set_periodic()
245 cr |= fttmr010->t1_enable_val; in fttmr010_timer_set_periodic()
246 writel(cr, fttmr010->base + TIMER_CR); in fttmr010_timer_set_periodic()
258 evt->event_handler(evt); in fttmr010_timer_interrupt()
267 writel(0x1, fttmr010->base + TIMER_INTR_STATE); in ast2600_timer_interrupt()
269 evt->event_handler(evt); in ast2600_timer_interrupt()
300 ret = -ENOMEM; in fttmr010_common_init()
303 fttmr010->tick_rate = clk_get_rate(clk); in fttmr010_common_init()
305 fttmr010->base = of_iomap(np, 0); in fttmr010_common_init()
306 if (!fttmr010->base) { in fttmr010_common_init()
308 ret = -ENXIO; in fttmr010_common_init()
315 ret = -EINVAL; in fttmr010_common_init()
320 * The Aspeed timers move bits around in the control register. in fttmr010_common_init()
323 fttmr010->t1_enable_val = TIMER_1_CR_ASPEED_ENABLE | in fttmr010_common_init()
325 fttmr010->is_aspeed = true; in fttmr010_common_init()
327 fttmr010->t1_enable_val = TIMER_1_CR_ENABLE | TIMER_1_CR_INT; in fttmr010_common_init()
332 writel(TIMER_INT_ALL_MASK, fttmr010->base + TIMER_INTR_MASK); in fttmr010_common_init()
333 writel(0, fttmr010->base + TIMER_INTR_STATE); in fttmr010_common_init()
346 writel(val, fttmr010->base + TIMER_CR); in fttmr010_common_init()
349 * Setup free-running clocksource timer (interrupts in fttmr010_common_init()
353 writel(0, fttmr010->base + TIMER2_COUNT); in fttmr010_common_init()
354 writel(0, fttmr010->base + TIMER2_MATCH1); in fttmr010_common_init()
355 writel(0, fttmr010->base + TIMER2_MATCH2); in fttmr010_common_init()
357 if (fttmr010->is_aspeed) { in fttmr010_common_init()
358 writel(~0, fttmr010->base + TIMER2_LOAD); in fttmr010_common_init()
359 clocksource_mmio_init(fttmr010->base + TIMER2_COUNT, in fttmr010_common_init()
360 "FTTMR010-TIMER2", in fttmr010_common_init()
361 fttmr010->tick_rate, in fttmr010_common_init()
364 fttmr010->tick_rate); in fttmr010_common_init()
366 writel(0, fttmr010->base + TIMER2_LOAD); in fttmr010_common_init()
367 clocksource_mmio_init(fttmr010->base + TIMER2_COUNT, in fttmr010_common_init()
368 "FTTMR010-TIMER2", in fttmr010_common_init()
369 fttmr010->tick_rate, in fttmr010_common_init()
372 fttmr010->tick_rate); in fttmr010_common_init()
376 * Setup clockevent timer (interrupt-driven) on timer 1. in fttmr010_common_init()
378 writel(0, fttmr010->base + TIMER1_COUNT); in fttmr010_common_init()
379 writel(0, fttmr010->base + TIMER1_LOAD); in fttmr010_common_init()
380 writel(0, fttmr010->base + TIMER1_MATCH1); in fttmr010_common_init()
381 writel(0, fttmr010->base + TIMER1_MATCH2); in fttmr010_common_init()
384 fttmr010->timer_shutdown = ast2600_timer_shutdown; in fttmr010_common_init()
386 IRQF_TIMER, "FTTMR010-TIMER1", in fttmr010_common_init()
387 &fttmr010->clkevt); in fttmr010_common_init()
389 fttmr010->timer_shutdown = fttmr010_timer_shutdown; in fttmr010_common_init()
391 IRQF_TIMER, "FTTMR010-TIMER1", in fttmr010_common_init()
392 &fttmr010->clkevt); in fttmr010_common_init()
395 pr_err("FTTMR010-TIMER1 no IRQ\n"); in fttmr010_common_init()
399 fttmr010->clkevt.name = "FTTMR010-TIMER1"; in fttmr010_common_init()
401 fttmr010->clkevt.rating = 300; in fttmr010_common_init()
402 fttmr010->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | in fttmr010_common_init()
404 fttmr010->clkevt.set_next_event = fttmr010_timer_set_next_event; in fttmr010_common_init()
405 fttmr010->clkevt.set_state_shutdown = fttmr010->timer_shutdown; in fttmr010_common_init()
406 fttmr010->clkevt.set_state_periodic = fttmr010_timer_set_periodic; in fttmr010_common_init()
407 fttmr010->clkevt.set_state_oneshot = fttmr010_timer_set_oneshot; in fttmr010_common_init()
408 fttmr010->clkevt.tick_resume = fttmr010->timer_shutdown; in fttmr010_common_init()
409 fttmr010->clkevt.cpumask = cpumask_of(0); in fttmr010_common_init()
410 fttmr010->clkevt.irq = irq; in fttmr010_common_init()
411 clockevents_config_and_register(&fttmr010->clkevt, in fttmr010_common_init()
412 fttmr010->tick_rate, in fttmr010_common_init()
417 if (fttmr010->is_aspeed) in fttmr010_common_init()
418 fttmr010->delay_timer.read_current_timer = in fttmr010_common_init()
421 fttmr010->delay_timer.read_current_timer = in fttmr010_common_init()
423 fttmr010->delay_timer.freq = fttmr010->tick_rate; in fttmr010_common_init()
424 register_current_timer_delay(&fttmr010->delay_timer); in fttmr010_common_init()
430 iounmap(fttmr010->base); in fttmr010_common_init()
455 TIMER_OF_DECLARE(gemini, "cortina,gemini-timer", fttmr010_timer_init);
456 TIMER_OF_DECLARE(moxart, "moxa,moxart-timer", fttmr010_timer_init);
457 TIMER_OF_DECLARE(ast2400, "aspeed,ast2400-timer", aspeed_timer_init);
458 TIMER_OF_DECLARE(ast2500, "aspeed,ast2500-timer", aspeed_timer_init);
459 TIMER_OF_DECLARE(ast2600, "aspeed,ast2600-timer", ast2600_timer_init);