3  * This file contains driver for the Cadence Triple Timer Counter Rev 06
7  * based on arch/mips/kernel/time.c timer driver
25  * T1: Timer 1, clocksource for generic timekeeping
26  * T2: Timer 2, clockevent source for hrtimers
27  * T3: Timer 3, <unused>
29  * The input frequency to the timer module for emulation is 2.5MHz which is
30  * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
33  * The input frequency to the timer module in silicon is configurable and
38  * Timer Register Offset Definitions of Timer 1, Increment base address by 4
39  * and use same offsets for Timer 2
67  * struct ttc_timer - This definition defines local timer structure
69  * @base_addr:	Base address of timer
70  * @freq:	Timer input clock frequency
105  * ttc_set_interval - Set the timer interval value
107  * @timer:	Pointer to the timer instance
108  * @cycles:	Timer interval ticks
110 static void ttc_set_interval(struct ttc_timer *timer,  in ttc_set_interval()  argument
116 	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_set_interval()
118 	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_set_interval()
120 	writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);  in ttc_set_interval()
128 	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_set_interval()
132  * ttc_clock_event_interrupt - Clock event timer interrupt handler
134  * @irq:	IRQ number of the Timer
142 	struct ttc_timer *timer = &ttce->ttc;  in ttc_clock_event_interrupt()  local
145 	readl_relaxed(timer->base_addr + TTC_ISR_OFFSET);  in ttc_clock_event_interrupt()
153  * __ttc_clocksource_read - Reads the timer counter register
156  * Returns: Current timer counter register value
160 	struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc;  in __ttc_clocksource_read()  local
162 	return (u64)readl_relaxed(timer->base_addr +  in __ttc_clocksource_read()
174  * @cycles:	Timer interval ticks
183 	struct ttc_timer *timer = &ttce->ttc;  in ttc_set_next_event()  local
185 	ttc_set_interval(timer, cycles);  in ttc_set_next_event()
190  * ttc_shutdown - Sets the state of timer
200 	struct ttc_timer *timer = &ttce->ttc;  in ttc_shutdown()  local
203 	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_shutdown()
205 	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_shutdown()
210  * ttc_set_periodic - Sets the state of timer
218 	struct ttc_timer *timer = &ttce->ttc;  in ttc_set_periodic()  local
220 	ttc_set_interval(timer,  in ttc_set_periodic()
228 	struct ttc_timer *timer = &ttce->ttc;  in ttc_resume()  local
231 	ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_resume()
233 	writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);  in ttc_resume()
272 		 * store timer clock ctrl register so we can restore it in case  in ttc_rate_change_clocksource_cb()
456 	 * Setup the clock event timer to be an interval timer which  in ttc_setup_clockevent()
490 	struct device_node *timer = pdev->dev.of_node;  in ttc_timer_probe()  local
498 	 * Get the 1st Triple Timer Counter (TTC) block from the device tree  in ttc_timer_probe()
499 	 * and use it. Note that the event timer uses the interrupt and it's the  in ttc_timer_probe()
502 	timer_baseaddr = devm_of_iomap(&pdev->dev, timer, 0, NULL);  in ttc_timer_probe()
504 		pr_err("ERROR: invalid timer base address\n");  in ttc_timer_probe()
508 	irq = irq_of_parse_and_map(timer, 1);  in ttc_timer_probe()
514 	of_property_read_u32(timer, "timer-width", &timer_width);  in ttc_timer_probe()
518 	clk_cs = of_clk_get(timer, clksel);  in ttc_timer_probe()
520 		pr_err("ERROR: timer input clock not found\n");  in ttc_timer_probe()
526 	clk_ce = of_clk_get(timer, clksel);  in ttc_timer_probe()
528 		pr_err("ERROR: timer input clock not found\n");  in ttc_timer_probe()
541 	pr_info("%pOFn #0 at %p, irq=%d\n", timer, timer_baseaddr, irq);  in ttc_timer_probe()