Lines Matching +full:rcar +full:- +full:gen2 +full:- +full:cmt0
1 // SPDX-License-Identifier: GPL-2.0
3 * SuperH Timer Support - CMT
39 * 16B 32B 32B-F 48B R-Car Gen2
40 * -----------------------------------------------------------------------------
46 * The r8a73a4 / R-Car Gen2 version has a per-channel start/stop register
50 * Channels are indexed from 0 to N-1 in the documentation. The channel index
55 * CMT0 on r8a7740, which is a 32-bit variant with a single channel numbered 0
59 * Similarly CMT0 on r8a73a4, r8a7790 and r8a7791, while implementing 32-bit
60 * channels only, is a 48-bit gen2 CMT with the 48-bit channels unavailable.
239 #define CMCLKE 0x1000 /* CLK Enable Register (R-Car Gen2) */
243 if (ch->iostart) in sh_cmt_read_cmstr()
244 return ch->cmt->info->read_control(ch->iostart, 0); in sh_cmt_read_cmstr()
246 return ch->cmt->info->read_control(ch->cmt->mapbase, 0); in sh_cmt_read_cmstr()
254 if (ch->iostart) { in sh_cmt_write_cmstr()
255 ch->cmt->info->write_control(ch->iostart, 0, value); in sh_cmt_write_cmstr()
256 udelay(ch->cmt->reg_delay); in sh_cmt_write_cmstr()
258 ch->cmt->info->write_control(ch->cmt->mapbase, 0, value); in sh_cmt_write_cmstr()
259 udelay(ch->cmt->reg_delay); in sh_cmt_write_cmstr()
266 return ch->cmt->info->read_control(ch->ioctrl, CMCSR); in sh_cmt_read_cmcsr()
274 ch->cmt->info->write_control(ch->ioctrl, CMCSR, value); in sh_cmt_write_cmcsr()
275 udelay(ch->cmt->reg_delay); in sh_cmt_write_cmcsr()
281 return ch->cmt->info->read_count(ch->ioctrl, CMCNT); in sh_cmt_read_cmcnt()
287 unsigned int cmcnt_delay = DIV_ROUND_UP(3 * ch->cmt->reg_delay, 2); in sh_cmt_write_cmcnt()
290 if (ch->cmt->info->model > SH_CMT_16BIT) { in sh_cmt_write_cmcnt()
298 ch->cmt->info->write_count(ch->ioctrl, CMCNT, value); in sh_cmt_write_cmcnt()
305 u32 old_value = ch->cmt->info->read_count(ch->ioctrl, CMCOR); in sh_cmt_write_cmcor()
308 ch->cmt->info->write_count(ch->ioctrl, CMCOR, value); in sh_cmt_write_cmcor()
309 udelay(ch->cmt->reg_delay); in sh_cmt_write_cmcor()
318 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; in sh_cmt_get_counter()
326 o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit; in sh_cmt_get_counter()
340 raw_spin_lock_irqsave(&ch->cmt->lock, flags); in sh_cmt_start_stop_ch()
344 value |= 1 << ch->timer_bit; in sh_cmt_start_stop_ch()
346 value &= ~(1 << ch->timer_bit); in sh_cmt_start_stop_ch()
349 raw_spin_unlock_irqrestore(&ch->cmt->lock, flags); in sh_cmt_start_stop_ch()
356 dev_pm_syscore_device(&ch->cmt->pdev->dev, true); in sh_cmt_enable()
359 ret = clk_enable(ch->cmt->clk); in sh_cmt_enable()
361 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n", in sh_cmt_enable()
362 ch->index); in sh_cmt_enable()
370 if (ch->cmt->info->width == 16) { in sh_cmt_enable()
374 u32 cmtout = ch->cmt->info->model <= SH_CMT_48BIT ? in sh_cmt_enable()
385 dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n", in sh_cmt_enable()
386 ch->index); in sh_cmt_enable()
387 ret = -ETIMEDOUT; in sh_cmt_enable()
396 clk_disable(ch->cmt->clk); in sh_cmt_enable()
411 clk_disable(ch->cmt->clk); in sh_cmt_disable()
413 dev_pm_syscore_device(&ch->cmt->pdev->dev, false); in sh_cmt_disable()
426 u32 value = ch->next_match_value; in sh_cmt_clock_event_program_verify()
433 ch->flags |= FLAG_REPROGRAM; /* force reprogram */ in sh_cmt_clock_event_program_verify()
437 * -> let the interrupt handler reprogram the timer. in sh_cmt_clock_event_program_verify()
438 * -> interrupt number two handles the event. in sh_cmt_clock_event_program_verify()
440 ch->flags |= FLAG_SKIPEVENT; in sh_cmt_clock_event_program_verify()
452 if (new_match > ch->max_match_value) in sh_cmt_clock_event_program_verify()
453 new_match = ch->max_match_value; in sh_cmt_clock_event_program_verify()
458 if (has_wrapped && (new_match > ch->match_value)) { in sh_cmt_clock_event_program_verify()
462 * -> first interrupt reprograms the timer. in sh_cmt_clock_event_program_verify()
463 * -> interrupt number two handles the event. in sh_cmt_clock_event_program_verify()
465 ch->flags |= FLAG_SKIPEVENT; in sh_cmt_clock_event_program_verify()
473 * -> save programmed match value. in sh_cmt_clock_event_program_verify()
474 * -> let isr handle the event. in sh_cmt_clock_event_program_verify()
476 ch->match_value = new_match; in sh_cmt_clock_event_program_verify()
484 * -> save programmed match value. in sh_cmt_clock_event_program_verify()
485 * -> let isr handle the event. in sh_cmt_clock_event_program_verify()
487 ch->match_value = new_match; in sh_cmt_clock_event_program_verify()
495 * -> increase delay and retry. in sh_cmt_clock_event_program_verify()
503 dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n", in sh_cmt_clock_event_program_verify()
504 ch->index); in sh_cmt_clock_event_program_verify()
511 if (delta > ch->max_match_value) in __sh_cmt_set_next()
512 dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n", in __sh_cmt_set_next()
513 ch->index); in __sh_cmt_set_next()
515 ch->next_match_value = delta; in __sh_cmt_set_next()
523 raw_spin_lock_irqsave(&ch->lock, flags); in sh_cmt_set_next()
525 raw_spin_unlock_irqrestore(&ch->lock, flags); in sh_cmt_set_next()
535 ch->cmt->info->clear_bits); in sh_cmt_interrupt()
541 if (ch->flags & FLAG_CLOCKSOURCE) in sh_cmt_interrupt()
542 ch->total_cycles += ch->match_value + 1; in sh_cmt_interrupt()
544 if (!(ch->flags & FLAG_REPROGRAM)) in sh_cmt_interrupt()
545 ch->next_match_value = ch->max_match_value; in sh_cmt_interrupt()
547 ch->flags |= FLAG_IRQCONTEXT; in sh_cmt_interrupt()
549 if (ch->flags & FLAG_CLOCKEVENT) { in sh_cmt_interrupt()
550 if (!(ch->flags & FLAG_SKIPEVENT)) { in sh_cmt_interrupt()
551 if (clockevent_state_oneshot(&ch->ced)) { in sh_cmt_interrupt()
552 ch->next_match_value = ch->max_match_value; in sh_cmt_interrupt()
553 ch->flags |= FLAG_REPROGRAM; in sh_cmt_interrupt()
556 ch->ced.event_handler(&ch->ced); in sh_cmt_interrupt()
560 ch->flags &= ~FLAG_SKIPEVENT; in sh_cmt_interrupt()
562 raw_spin_lock_irqsave(&ch->lock, flags); in sh_cmt_interrupt()
564 if (ch->flags & FLAG_REPROGRAM) { in sh_cmt_interrupt()
565 ch->flags &= ~FLAG_REPROGRAM; in sh_cmt_interrupt()
568 if (ch->flags & FLAG_CLOCKEVENT) in sh_cmt_interrupt()
569 if ((clockevent_state_shutdown(&ch->ced)) in sh_cmt_interrupt()
570 || (ch->match_value == ch->next_match_value)) in sh_cmt_interrupt()
571 ch->flags &= ~FLAG_REPROGRAM; in sh_cmt_interrupt()
574 ch->flags &= ~FLAG_IRQCONTEXT; in sh_cmt_interrupt()
576 raw_spin_unlock_irqrestore(&ch->lock, flags); in sh_cmt_interrupt()
587 pm_runtime_get_sync(&ch->cmt->pdev->dev); in sh_cmt_start()
589 raw_spin_lock_irqsave(&ch->lock, flags); in sh_cmt_start()
591 if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) { in sh_cmt_start()
593 pm_runtime_get_sync(&ch->cmt->pdev->dev); in sh_cmt_start()
599 ch->flags |= flag; in sh_cmt_start()
602 if (ch->cmt->num_channels == 1 && in sh_cmt_start()
603 flag == FLAG_CLOCKSOURCE && (!(ch->flags & FLAG_CLOCKEVENT))) in sh_cmt_start()
604 __sh_cmt_set_next(ch, ch->max_match_value); in sh_cmt_start()
606 raw_spin_unlock_irqrestore(&ch->lock, flags); in sh_cmt_start()
616 raw_spin_lock_irqsave(&ch->lock, flags); in sh_cmt_stop()
618 f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE); in sh_cmt_stop()
619 ch->flags &= ~flag; in sh_cmt_stop()
621 if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) { in sh_cmt_stop()
624 pm_runtime_put(&ch->cmt->pdev->dev); in sh_cmt_stop()
628 if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE)) in sh_cmt_stop()
629 __sh_cmt_set_next(ch, ch->max_match_value); in sh_cmt_stop()
631 raw_spin_unlock_irqrestore(&ch->lock, flags); in sh_cmt_stop()
634 pm_runtime_put(&ch->cmt->pdev->dev); in sh_cmt_stop()
647 if (ch->cmt->num_channels == 1) { in sh_cmt_clocksource_read()
652 raw_spin_lock_irqsave(&ch->lock, flags); in sh_cmt_clocksource_read()
653 value = ch->total_cycles; in sh_cmt_clocksource_read()
657 raw += ch->match_value + 1; in sh_cmt_clocksource_read()
658 raw_spin_unlock_irqrestore(&ch->lock, flags); in sh_cmt_clocksource_read()
671 WARN_ON(ch->cs_enabled); in sh_cmt_clocksource_enable()
673 ch->total_cycles = 0; in sh_cmt_clocksource_enable()
677 ch->cs_enabled = true; in sh_cmt_clocksource_enable()
686 WARN_ON(!ch->cs_enabled); in sh_cmt_clocksource_disable()
689 ch->cs_enabled = false; in sh_cmt_clocksource_disable()
696 if (!ch->cs_enabled) in sh_cmt_clocksource_suspend()
700 dev_pm_genpd_suspend(&ch->cmt->pdev->dev); in sh_cmt_clocksource_suspend()
707 if (!ch->cs_enabled) in sh_cmt_clocksource_resume()
710 dev_pm_genpd_resume(&ch->cmt->pdev->dev); in sh_cmt_clocksource_resume()
717 struct clocksource *cs = &ch->cs; in sh_cmt_register_clocksource()
719 cs->name = name; in sh_cmt_register_clocksource()
720 cs->rating = 125; in sh_cmt_register_clocksource()
721 cs->read = sh_cmt_clocksource_read; in sh_cmt_register_clocksource()
722 cs->enable = sh_cmt_clocksource_enable; in sh_cmt_register_clocksource()
723 cs->disable = sh_cmt_clocksource_disable; in sh_cmt_register_clocksource()
724 cs->suspend = sh_cmt_clocksource_suspend; in sh_cmt_register_clocksource()
725 cs->resume = sh_cmt_clocksource_resume; in sh_cmt_register_clocksource()
726 cs->mask = CLOCKSOURCE_MASK(ch->cmt->info->width); in sh_cmt_register_clocksource()
727 cs->flags = CLOCK_SOURCE_IS_CONTINUOUS; in sh_cmt_register_clocksource()
729 dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n", in sh_cmt_register_clocksource()
730 ch->index); in sh_cmt_register_clocksource()
732 clocksource_register_hz(cs, ch->cmt->rate); in sh_cmt_register_clocksource()
746 sh_cmt_set_next(ch, ((ch->cmt->rate + HZ/2) / HZ) - 1); in sh_cmt_clock_event_start()
748 sh_cmt_set_next(ch, ch->max_match_value); in sh_cmt_clock_event_start()
768 dev_info(&ch->cmt->pdev->dev, "ch%u: used for %s clock events\n", in sh_cmt_clock_event_set_state()
769 ch->index, periodic ? "periodic" : "oneshot"); in sh_cmt_clock_event_set_state()
792 raw_spin_lock_irqsave(&ch->lock, flags); in sh_cmt_clock_event_next()
794 if (likely(ch->flags & FLAG_IRQCONTEXT)) in sh_cmt_clock_event_next()
795 ch->next_match_value = delta - 1; in sh_cmt_clock_event_next()
797 __sh_cmt_set_next(ch, delta - 1); in sh_cmt_clock_event_next()
799 raw_spin_unlock_irqrestore(&ch->lock, flags); in sh_cmt_clock_event_next()
808 dev_pm_genpd_suspend(&ch->cmt->pdev->dev); in sh_cmt_clock_event_suspend()
809 clk_unprepare(ch->cmt->clk); in sh_cmt_clock_event_suspend()
816 clk_prepare(ch->cmt->clk); in sh_cmt_clock_event_resume()
817 dev_pm_genpd_resume(&ch->cmt->pdev->dev); in sh_cmt_clock_event_resume()
823 struct clock_event_device *ced = &ch->ced; in sh_cmt_register_clockevent()
827 irq = platform_get_irq(ch->cmt->pdev, ch->index); in sh_cmt_register_clockevent()
833 dev_name(&ch->cmt->pdev->dev), ch); in sh_cmt_register_clockevent()
835 dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n", in sh_cmt_register_clockevent()
836 ch->index, irq); in sh_cmt_register_clockevent()
840 ced->name = name; in sh_cmt_register_clockevent()
841 ced->features = CLOCK_EVT_FEAT_PERIODIC; in sh_cmt_register_clockevent()
842 ced->features |= CLOCK_EVT_FEAT_ONESHOT; in sh_cmt_register_clockevent()
843 ced->rating = 125; in sh_cmt_register_clockevent()
844 ced->cpumask = cpu_possible_mask; in sh_cmt_register_clockevent()
845 ced->set_next_event = sh_cmt_clock_event_next; in sh_cmt_register_clockevent()
846 ced->set_state_shutdown = sh_cmt_clock_event_shutdown; in sh_cmt_register_clockevent()
847 ced->set_state_periodic = sh_cmt_clock_event_set_periodic; in sh_cmt_register_clockevent()
848 ced->set_state_oneshot = sh_cmt_clock_event_set_oneshot; in sh_cmt_register_clockevent()
849 ced->suspend = sh_cmt_clock_event_suspend; in sh_cmt_register_clockevent()
850 ced->resume = sh_cmt_clock_event_resume; in sh_cmt_register_clockevent()
853 ced->shift = 32; in sh_cmt_register_clockevent()
854 ced->mult = div_sc(ch->cmt->rate, NSEC_PER_SEC, ced->shift); in sh_cmt_register_clockevent()
855 ced->max_delta_ns = clockevent_delta2ns(ch->max_match_value, ced); in sh_cmt_register_clockevent()
856 ced->max_delta_ticks = ch->max_match_value; in sh_cmt_register_clockevent()
857 ced->min_delta_ns = clockevent_delta2ns(0x1f, ced); in sh_cmt_register_clockevent()
858 ced->min_delta_ticks = 0x1f; in sh_cmt_register_clockevent()
860 dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n", in sh_cmt_register_clockevent()
861 ch->index); in sh_cmt_register_clockevent()
873 ch->cmt->has_clockevent = true; in sh_cmt_register()
880 ch->cmt->has_clocksource = true; in sh_cmt_register()
898 ch->cmt = cmt; in sh_cmt_setup_channel()
899 ch->index = index; in sh_cmt_setup_channel()
900 ch->hwidx = hwidx; in sh_cmt_setup_channel()
901 ch->timer_bit = hwidx; in sh_cmt_setup_channel()
905 * timers with a per-channel start/stop register, compute its address in sh_cmt_setup_channel()
908 switch (cmt->info->model) { in sh_cmt_setup_channel()
910 ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6; in sh_cmt_setup_channel()
914 ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10; in sh_cmt_setup_channel()
918 ch->iostart = cmt->mapbase + ch->hwidx * 0x100; in sh_cmt_setup_channel()
919 ch->ioctrl = ch->iostart + 0x10; in sh_cmt_setup_channel()
920 ch->timer_bit = 0; in sh_cmt_setup_channel()
923 value = ioread32(cmt->mapbase + CMCLKE); in sh_cmt_setup_channel()
925 iowrite32(value, cmt->mapbase + CMCLKE); in sh_cmt_setup_channel()
929 if (cmt->info->width == (sizeof(ch->max_match_value) * 8)) in sh_cmt_setup_channel()
930 ch->max_match_value = ~0; in sh_cmt_setup_channel()
932 ch->max_match_value = (1 << cmt->info->width) - 1; in sh_cmt_setup_channel()
934 ch->match_value = ch->max_match_value; in sh_cmt_setup_channel()
935 raw_spin_lock_init(&ch->lock); in sh_cmt_setup_channel()
937 ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev), in sh_cmt_setup_channel()
940 dev_err(&cmt->pdev->dev, "ch%u: registration failed\n", in sh_cmt_setup_channel()
941 ch->index); in sh_cmt_setup_channel()
944 ch->cs_enabled = false; in sh_cmt_setup_channel()
953 mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0); in sh_cmt_map_memory()
955 dev_err(&cmt->pdev->dev, "failed to get I/O memory\n"); in sh_cmt_map_memory()
956 return -ENXIO; in sh_cmt_map_memory()
959 cmt->mapbase = ioremap(mem->start, resource_size(mem)); in sh_cmt_map_memory()
960 if (cmt->mapbase == NULL) { in sh_cmt_map_memory()
961 dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n"); in sh_cmt_map_memory()
962 return -ENXIO; in sh_cmt_map_memory()
969 { "sh-cmt-16", (kernel_ulong_t)&sh_cmt_info[SH_CMT_16BIT] },
970 { "sh-cmt-32", (kernel_ulong_t)&sh_cmt_info[SH_CMT_32BIT] },
978 .compatible = "renesas,cmt-48",
983 .compatible = "renesas,cmt-48-gen2",
987 .compatible = "renesas,r8a7740-cmt1",
991 .compatible = "renesas,sh73a0-cmt1",
995 .compatible = "renesas,rcar-gen2-cmt0",
999 .compatible = "renesas,rcar-gen2-cmt1",
1003 .compatible = "renesas,rcar-gen3-cmt0",
1007 .compatible = "renesas,rcar-gen3-cmt1",
1011 .compatible = "renesas,rcar-gen4-cmt0",
1015 .compatible = "renesas,rcar-gen4-cmt1",
1028 cmt->pdev = pdev; in sh_cmt_setup()
1029 raw_spin_lock_init(&cmt->lock); in sh_cmt_setup()
1031 if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node) { in sh_cmt_setup()
1032 cmt->info = of_device_get_match_data(&pdev->dev); in sh_cmt_setup()
1033 cmt->hw_channels = cmt->info->channels_mask; in sh_cmt_setup()
1034 } else if (pdev->dev.platform_data) { in sh_cmt_setup()
1035 struct sh_timer_config *cfg = pdev->dev.platform_data; in sh_cmt_setup()
1036 const struct platform_device_id *id = pdev->id_entry; in sh_cmt_setup()
1038 cmt->info = (const struct sh_cmt_info *)id->driver_data; in sh_cmt_setup()
1039 cmt->hw_channels = cfg->channels_mask; in sh_cmt_setup()
1041 dev_err(&cmt->pdev->dev, "missing platform data\n"); in sh_cmt_setup()
1042 return -ENXIO; in sh_cmt_setup()
1046 cmt->clk = clk_get(&cmt->pdev->dev, "fck"); in sh_cmt_setup()
1047 if (IS_ERR(cmt->clk)) { in sh_cmt_setup()
1048 dev_err(&cmt->pdev->dev, "cannot get clock\n"); in sh_cmt_setup()
1049 return PTR_ERR(cmt->clk); in sh_cmt_setup()
1052 ret = clk_prepare(cmt->clk); in sh_cmt_setup()
1057 ret = clk_enable(cmt->clk); in sh_cmt_setup()
1061 rate = clk_get_rate(cmt->clk); in sh_cmt_setup()
1063 ret = -EINVAL; in sh_cmt_setup()
1068 if (cmt->info->model >= SH_CMT_48BIT) in sh_cmt_setup()
1069 cmt->reg_delay = DIV_ROUND_UP(2UL * USEC_PER_SEC, rate); in sh_cmt_setup()
1070 cmt->rate = rate / (cmt->info->width == 16 ? 512 : 8); in sh_cmt_setup()
1078 cmt->num_channels = hweight8(cmt->hw_channels); in sh_cmt_setup()
1079 cmt->channels = kcalloc(cmt->num_channels, sizeof(*cmt->channels), in sh_cmt_setup()
1081 if (cmt->channels == NULL) { in sh_cmt_setup()
1082 ret = -ENOMEM; in sh_cmt_setup()
1090 for (i = 0, mask = cmt->hw_channels; i < cmt->num_channels; ++i) { in sh_cmt_setup()
1091 unsigned int hwidx = ffs(mask) - 1; in sh_cmt_setup()
1092 bool clocksource = i == 1 || cmt->num_channels == 1; in sh_cmt_setup()
1095 ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx, in sh_cmt_setup()
1103 clk_disable(cmt->clk); in sh_cmt_setup()
1110 kfree(cmt->channels); in sh_cmt_setup()
1111 iounmap(cmt->mapbase); in sh_cmt_setup()
1113 clk_disable(cmt->clk); in sh_cmt_setup()
1115 clk_unprepare(cmt->clk); in sh_cmt_setup()
1117 clk_put(cmt->clk); in sh_cmt_setup()
1127 pm_runtime_set_active(&pdev->dev); in sh_cmt_probe()
1128 pm_runtime_enable(&pdev->dev); in sh_cmt_probe()
1132 dev_info(&pdev->dev, "kept as earlytimer\n"); in sh_cmt_probe()
1138 return -ENOMEM; in sh_cmt_probe()
1143 pm_runtime_idle(&pdev->dev); in sh_cmt_probe()
1150 if (cmt->has_clockevent || cmt->has_clocksource) in sh_cmt_probe()
1151 pm_runtime_irq_safe(&pdev->dev); in sh_cmt_probe()
1153 pm_runtime_idle(&pdev->dev); in sh_cmt_probe()