1 // SPDX-License-Identifier: GPL-2.0-only
2 /* linux/arch/arm/mach-exynos4/mct.c
7  * Exynos4 MCT(Multi-Core Timer) support
70 #define MCT_NR_LOCAL	(MCT_NR_IRQS - MCT_L0_IRQ)
167  * exynos4_read_count_64 - Read all 64-bits of the global counter
169  * This will read all 64-bits of the global counter taking care to make sure
171  * slow (hundreds of nanoseconds) so you should use the 32-bit (lower half
191  * exynos4_read_count_32 - Read the lower 32-bits of the global counter
193  * This will read just the lower 32-bits of the global counter.  This is marked
214 	.name		= "mct-frc",
233 			 "cycles_t needs to move to 32-bit for ARM64 usage");  in exynos4_read_current_timer()
241 	 * When the frc is shared, the main processer should have already  in exynos4_clocksource_init()
314 	cycles_per_jiffy = (((unsigned long long)NSEC_PER_SEC / HZ * evt->mult)  in mct_set_state_periodic()
315 			    >> evt->shift);  in mct_set_state_periodic()
322 	.name			= "mct-comp",
340 	evt->event_handler(evt);  in exynos4_mct_comp_isr()
365 	unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;  in exynos4_mct_tick_stop()
384 	exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);  in exynos4_mct_tick_start()
387 	exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);  in exynos4_mct_tick_start()
389 	tmp = readl_relaxed(reg_base + mevt->base + MCT_L_TCON_OFFSET);  in exynos4_mct_tick_start()
392 	exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);  in exynos4_mct_tick_start()
398 	if (readl_relaxed(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1)  in exynos4_mct_tick_clear()
399 		exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);  in exynos4_mct_tick_clear()
428 	cycles_per_jiffy = (((unsigned long long)NSEC_PER_SEC / HZ * evt->mult)  in set_state_periodic()
429 			    >> evt->shift);  in set_state_periodic()
438 	struct clock_event_device *evt = &mevt->evt;  in exynos4_mct_tick_isr()
445 	if (!clockevent_state_periodic(&mevt->evt))  in exynos4_mct_tick_isr()
450 	evt->event_handler(evt);  in exynos4_mct_tick_isr()
459 	struct clock_event_device *evt = &mevt->evt;  in exynos4_mct_starting_cpu()
461 	snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu);  in exynos4_mct_starting_cpu()
463 	evt->name = mevt->name;  in exynos4_mct_starting_cpu()
464 	evt->cpumask = cpumask_of(cpu);  in exynos4_mct_starting_cpu()
465 	evt->set_next_event = exynos4_tick_set_next_event;  in exynos4_mct_starting_cpu()
466 	evt->set_state_periodic = set_state_periodic;  in exynos4_mct_starting_cpu()
467 	evt->set_state_shutdown = set_state_shutdown;  in exynos4_mct_starting_cpu()
468 	evt->set_state_oneshot = set_state_shutdown;  in exynos4_mct_starting_cpu()
469 	evt->set_state_oneshot_stopped = set_state_shutdown;  in exynos4_mct_starting_cpu()
470 	evt->tick_resume = set_state_shutdown;  in exynos4_mct_starting_cpu()
471 	evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |  in exynos4_mct_starting_cpu()
473 	evt->rating = MCT_CLKEVENTS_RATING;  in exynos4_mct_starting_cpu()
475 	exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);  in exynos4_mct_starting_cpu()
479 		if (evt->irq == -1)  in exynos4_mct_starting_cpu()
480 			return -EIO;  in exynos4_mct_starting_cpu()
482 		irq_force_affinity(evt->irq, cpumask_of(cpu));  in exynos4_mct_starting_cpu()
483 		enable_irq(evt->irq);  in exynos4_mct_starting_cpu()
497 	struct clock_event_device *evt = &mevt->evt;  in exynos4_mct_dying_cpu()
499 	evt->set_state_shutdown(evt);  in exynos4_mct_dying_cpu()
501 		if (evt->irq != -1)  in exynos4_mct_dying_cpu()
502 			disable_irq_nosync(evt->irq);  in exynos4_mct_dying_cpu()
503 		exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);  in exynos4_mct_dying_cpu()
532  * exynos4_timer_interrupts - initialize MCT interrupts
557 		pr_err("exynos-mct: too many (%d) interrupts configured in DT\n",  in exynos4_timer_interrupts()
579 				err = -EINVAL;  in exynos4_timer_interrupts()
585 			pcpu_mevt->evt.irq = -1;  in exynos4_timer_interrupts()
594 					pcpu_mevt->name, pcpu_mevt)) {  in exynos4_timer_interrupts()
595 				pr_err("exynos-mct: cannot register IRQ (cpu%d)\n",  in exynos4_timer_interrupts()
600 			pcpu_mevt->evt.irq = mct_irq;  in exynos4_timer_interrupts()
608 			err = -EINVAL;  in exynos4_timer_interrupts()
612 		mevt->base = EXYNOS4_MCT_L_BASE(local_idx[cpu]);  in exynos4_timer_interrupts()
633 			if (pcpu_mevt->evt.irq != -1) {  in exynos4_timer_interrupts()
634 				free_irq(pcpu_mevt->evt.irq, pcpu_mevt);  in exynos4_timer_interrupts()
635 				pcpu_mevt->evt.irq = -1;  in exynos4_timer_interrupts()
644 	bool frc_shared = of_property_read_bool(np, "samsung,frc-shared");  in mct_init_dt()
649 	nr_local = of_property_count_u32_elems(np, "samsung,local-timers");  in mct_init_dt()
651 		return -EINVAL;  in mct_init_dt()
654 			return -EINVAL;  in mct_init_dt()
656 		ret = of_property_read_u32_array(np, "samsung,local-timers",  in mct_init_dt()
681 	 * When the FRC is shared with a main processor, this secondary  in mct_init_dt()
700 TIMER_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi);
701 TIMER_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);