Lines Matching +full:0 +full:x2c00
23 * 0x0 - plain read write mode
24 * 0x4 - set mode, OR logic.
25 * 0x8 - clr mode, XOR logic.
26 * 0xc - togle mode.
31 #define HW_IR 0x0000 /* RW. Interrupt */
36 #define BM_IR_MR0 BIT(0)
38 #define HW_TCR 0x0010 /* RW. Timer controller */
49 * 0 - counters are disabled */
53 #define BM_C0_EN BIT(0)
55 #define HW_DIR 0x0020 /* RW. Direction? */
59 #define BM_DIR_COUNT_UP 0
61 #define BM_DIR0_SHIFT 0
70 #define HW_TC0 0x0030 /* RO. Timer counter 0 */
71 /* HW_TC*. Timer counter owerflow (0xffff.ffff to 0x0000.0000) do not generate
73 #define HW_TC1 0x0040
74 #define HW_TC2 0x0050
75 #define HW_TC3 0x0060
77 #define HW_PR 0x0070 /* RW. prescaler */
78 #define BM_PR_DISABLE 0
79 #define HW_PC 0x0080 /* RO. Prescaler counter */
80 #define HW_MCR 0x0090 /* RW. Match control */
82 #define BM_MCR_INT_EN(n) (1 << (n * 3 + 0))
88 #define HW_MR0 0x00a0 /* RW. Match reg */
89 #define HW_MR1 0x00b0
90 #define HW_MR2 0x00C0
91 #define HW_MR3 0x00D0
93 #define HW_CTCR 0x0180 /* Counter control */
94 #define BM_CTCR0_SHIFT 0
98 #define BM_CTCR_TM 0 /* Timer mode. Every rising PCLK edge. */
116 return 0; in asm9260_timer_set_next_event()
128 return 0; in asm9260_timer_shutdown()
136 writel_relaxed(BM_MCR_RES_EN(0) | BM_MCR_STOP_EN(0), in asm9260_timer_set_oneshot()
138 return 0; in asm9260_timer_set_oneshot()
146 writel_relaxed(BM_MCR_RES_EN(0) | BM_MCR_STOP_EN(0), in asm9260_timer_set_periodic()
152 return 0; in asm9260_timer_set_periodic()
190 priv.base = of_io_request_and_map(np, 0, np->name); in asm9260_timer_init()
196 clk = of_clk_get(np, 0); in asm9260_timer_init()
208 irq = irq_of_parse_and_map(np, 0); in asm9260_timer_init()
224 writel_relaxed(BM_MCR_INT_EN(0) , priv.base + HW_MCR); in asm9260_timer_init()
232 writel_relaxed(0xffffffff, priv.base + HW_MR1); in asm9260_timer_init()
237 event_dev.cpumask = cpumask_of(0); in asm9260_timer_init()
238 clockevents_config_and_register(&event_dev, rate, 0x2c00, 0xfffffffe); in asm9260_timer_init()
240 return 0; in asm9260_timer_init()