Lines Matching +full:prcmu +full:- +full:internal
1 # SPDX-License-Identifier: GPL-2.0-only
60 bool "OMAP dual-mode timer driver" if ARCH_K3 || COMPILE_TEST
64 Enables the support for the TI dual-mode timer driver.
190 Enable 24-bit TIMER0 and TIMER1 counters in the NPCM7xx architecture,
213 32-bit free running decrementing counters.
216 bool "Clocksource PRCMU Timer" if COMPILE_TEST
219 Use the always on PRCMU Timer as clocksource.
248 bool "Integrator-AP timer driver" if COMPILE_TEST
251 Enables support for the Integrator-AP timer.
276 available on many OMAP-like platforms.
295 bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST
299 These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores
304 bool "Support for 64-bit counters in ARC HS38 cores" if COMPILE_TEST
308 This enables 2 different 64-bit timers: RTC (for UP) and GFRC (for SMP).
326 power-of-2 divisor of the clock rate. The behaviour can also be
329 The main use of the event stream is wfe-based timeouts of userspace
340 bool "Workaround for Freescale/NXP Erratum A-008585"
346 A-008585 ("ARM generic timer may contain an erroneous
348 fsl,erratum-a008585 property is found in the timer node.
357 161010101. The workaround will be active if the hisilicon,erratum-161010101
361 bool "Workaround for Cortex-A73 erratum 858921"
366 This option enables a workaround applicable to Cortex-A73
379 allwinner,erratum-unknown1 property is found in the timer node.
396 change, the driver tries to fix the timer's internal prescaler.
513 bool "J-Core PIT timer driver" if COMPILE_TEST
519 the integrated PIT in the J-Core synthesizable, open source SoC.
527 the Compare Match Timer (CMT) hardware available in 16/32/48-bit
535 This enables build of a clockevent driver for the Multi-Function
537 This hardware comes with 16-bit timer registers.
553 the 32-bit Timer Unit (TMU) hardware available on a wide range
562 the 48-bit System Timer (STI) hardware available on a SoCs
590 bool "Clocksource for PXA or SA-11x0 platform" if COMPILE_TEST
594 This enables OST0 support available on PXA and SA-11x0
645 bool "Timer for the RISC-V platform" if COMPILE_TEST
650 This enables the per-hart timer built into all RISC-V systems, which
652 required for all RISC-V systems.
655 bool "CLINT Timer for the RISC-V platform" if COMPILE_TEST
660 This option enables the CLINT timer for RISC-V systems. The CLINT
661 driver is usually used for NoMMU RISC-V systems.
664 bool "SMP Timer for the C-SKY platform" if COMPILE_TEST
668 Say yes here to enable C-SKY SMP timer driver used for C-SKY SMP
697 programmable 32-bit free running incrementing counters.
739 bool "Clocksource using goldfish-rtc"
743 Support for the timer/counter of goldfish-rtc