1 // SPDX-License-Identifier: GPL-2.0
5  *  Copyright (C) 2016-2018 Xilinx
9 #include <linux/clk-provider.h>
11 #include "clk-zynqmp.h"
14  * struct zynqmp_pll - PLL clock
15  * @hw:		Handle between common and hardware-specific interfaces
44  * zynqmp_pll_get_mode() - Get mode of PLL
45  * @hw:		Handle between common and hardware-specific interfaces
52 	u32 clk_id = clk->clk_id;  in zynqmp_pll_get_mode()
68  * zynqmp_pll_set_mode() - Set the PLL mode
69  * @hw:		Handle between common and hardware-specific interfaces
75 	u32 clk_id = clk->clk_id;  in zynqmp_pll_set_mode()
87 		pr_debug("%s() PLL set frac mode failed for %s, ret = %d\n",  in zynqmp_pll_set_mode()
90 		clk->set_pll_mode = true;  in zynqmp_pll_set_mode()
94  * zynqmp_pll_round_rate() - Round a clock frequency
95  * @hw:		Handle between common and hardware-specific interfaces
96  * @rate:	Desired clock frequency
97  * @prate:	Clock frequency of parent clock
99  * Return: Frequency closest to @rate the hardware can generate
107 	/* Let rate fall inside the range PS_PLL_VCO_MIN ~ PS_PLL_VCO_MAX */  in zynqmp_pll_determine_rate()
108 	if (req->rate > PS_PLL_VCO_MAX) {  in zynqmp_pll_determine_rate()
109 		div = DIV_ROUND_UP(req->rate, PS_PLL_VCO_MAX);  in zynqmp_pll_determine_rate()
110 		req->rate = req->rate / div;  in zynqmp_pll_determine_rate()
112 	if (req->rate < PS_PLL_VCO_MIN) {  in zynqmp_pll_determine_rate()
113 		mult = DIV_ROUND_UP(PS_PLL_VCO_MIN, req->rate);  in zynqmp_pll_determine_rate()
114 		req->rate = req->rate * mult;  in zynqmp_pll_determine_rate()
117 	fbdiv = DIV_ROUND_CLOSEST(req->rate, req->best_parent_rate);  in zynqmp_pll_determine_rate()
120 		req->rate = req->best_parent_rate * fbdiv;  in zynqmp_pll_determine_rate()
127  * zynqmp_pll_recalc_rate() - Recalculate clock frequency
128  * @hw:			Handle between common and hardware-specific interfaces
129  * @parent_rate:	Clock frequency of parent clock
137 	u32 clk_id = clk->clk_id;  in zynqmp_pll_recalc_rate()
140 	unsigned long rate, frac;  in zynqmp_pll_recalc_rate()  local
156 	rate =  parent_rate * fbdiv;  in zynqmp_pll_recalc_rate()
161 		rate = rate + frac;  in zynqmp_pll_recalc_rate()
164 	return rate;  in zynqmp_pll_recalc_rate()
168  * zynqmp_pll_set_rate() - Set rate of PLL
169  * @hw:			Handle between common and hardware-specific interfaces
170  * @rate:		Frequency of clock to be set
171  * @parent_rate:	Clock frequency of parent clock
173  * Set PLL divider to set desired rate.
175  * Returns:            rate which is set on success else error code
177 static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate,  in zynqmp_pll_set_rate()  argument
181 	u32 clk_id = clk->clk_id;  in zynqmp_pll_set_rate()
187 	rate_div = (rate * FRAC_DIV) / parent_rate;  in zynqmp_pll_set_rate()
194 		rate = parent_rate * m;  in zynqmp_pll_set_rate()
198 		if (ret == -EUSERS)  in zynqmp_pll_set_rate()
202 			pr_debug("%s() set divider failed for %s, ret = %d\n",  in zynqmp_pll_set_rate()
206 		return rate + frac;  in zynqmp_pll_set_rate()
209 	fbdiv = DIV_ROUND_CLOSEST(rate, parent_rate);  in zynqmp_pll_set_rate()
213 		pr_debug("%s() set divider failed for %s, ret = %d\n",  in zynqmp_pll_set_rate()
220  * zynqmp_pll_is_enabled() - Check if a clock is enabled
221  * @hw:		Handle between common and hardware-specific interfaces
229 	u32 clk_id = clk->clk_id;  in zynqmp_pll_is_enabled()
237 		return -EIO;  in zynqmp_pll_is_enabled()
244  * zynqmp_pll_enable() - Enable clock
245  * @hw:		Handle between common and hardware-specific interfaces
253 	u32 clk_id = clk->clk_id;  in zynqmp_pll_enable()
260 	if (zynqmp_pll_is_enabled(hw) && (!clk->set_pll_mode))  in zynqmp_pll_enable()
263 	clk->set_pll_mode = false;  in zynqmp_pll_enable()
274  * zynqmp_pll_disable() - Disable clock
275  * @hw:		Handle between common and hardware-specific interfaces
281 	u32 clk_id = clk->clk_id;  in zynqmp_pll_disable()
303  * zynqmp_clk_register_pll() - Register PLL with the clock framework
325 	init.flags = zynqmp_clk_map_common_ccf_flags(nodes->flag);  in zynqmp_clk_register_pll()
332 		return ERR_PTR(-ENOMEM);  in zynqmp_clk_register_pll()
334 	pll->hw.init = &init;  in zynqmp_clk_register_pll()
335 	pll->clk_id = clk_id;  in zynqmp_clk_register_pll()
337 	hw = &pll->hw;  in zynqmp_clk_register_pll()