96  * @rate:	Desired clock frequency
99  * Return: Frequency closest to @rate the hardware can generate
101 static long zynqmp_pll_round_rate(struct clk_hw *hw, unsigned long rate,  in zynqmp_pll_round_rate()  argument
107 	/* Let rate fall inside the range PS_PLL_VCO_MIN ~ PS_PLL_VCO_MAX */  in zynqmp_pll_round_rate()
108 	if (rate > PS_PLL_VCO_MAX) {  in zynqmp_pll_round_rate()
109 		div = DIV_ROUND_UP(rate, PS_PLL_VCO_MAX);  in zynqmp_pll_round_rate()
110 		rate = rate / div;  in zynqmp_pll_round_rate()
112 	if (rate < PS_PLL_VCO_MIN) {  in zynqmp_pll_round_rate()
113 		mult = DIV_ROUND_UP(PS_PLL_VCO_MIN, rate);  in zynqmp_pll_round_rate()
114 		rate = rate * mult;  in zynqmp_pll_round_rate()
117 	fbdiv = DIV_ROUND_CLOSEST(rate, *prate);  in zynqmp_pll_round_rate()
120 		rate = *prate * fbdiv;  in zynqmp_pll_round_rate()
123 	return rate;  in zynqmp_pll_round_rate()
140 	unsigned long rate, frac;  in zynqmp_pll_recalc_rate()  local
156 	rate =  parent_rate * fbdiv;  in zynqmp_pll_recalc_rate()
161 		rate = rate + frac;  in zynqmp_pll_recalc_rate()
164 	return rate;  in zynqmp_pll_recalc_rate()
168  * zynqmp_pll_set_rate() - Set rate of PLL
170  * @rate:		Frequency of clock to be set
173  * Set PLL divider to set desired rate.
175  * Returns:            rate which is set on success else error code
177 static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate,  in zynqmp_pll_set_rate()  argument
187 	rate_div = (rate * FRAC_DIV) / parent_rate;  in zynqmp_pll_set_rate()
194 		rate = parent_rate * m;  in zynqmp_pll_set_rate()
206 		return rate + frac;  in zynqmp_pll_set_rate()
209 	fbdiv = DIV_ROUND_CLOSEST(rate, parent_rate);  in zynqmp_pll_set_rate()