1 // SPDX-License-Identifier: GPL-2.0
5  *  Copyright (C) 2016-2019 Xilinx
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
13 #include "clk-zynqmp.h"
19  * prepare - clk_prepare only ensures that parents are prepared
20  * enable - clk_enable only ensures that parents are enabled
21  * rate - rate is adjustable.  clk->rate = ceiling(parent->rate / divisor)
22  * parent - fixed parent.  No clk_set_parent support
32  * struct zynqmp_clk_divider - adjustable divider clock
33  * @hw:		handle between common and hardware-specific interfaces
65 		return (rate - up_rate) <= (down_rate - rate) ? up : down;  in zynqmp_divider_get_val()
73  * zynqmp_clk_divider_recalc_rate() - Recalc rate of divider clock
74  * @hw:			handle between common and hardware-specific interfaces
84 	u32 clk_id = divider->clk_id;  in zynqmp_clk_divider_recalc_rate()
85 	u32 div_type = divider->div_type;  in zynqmp_clk_divider_recalc_rate()
100 	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)  in zynqmp_clk_divider_recalc_rate()
104 		WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),  in zynqmp_clk_divider_recalc_rate()
114  * zynqmp_clk_divider_round_rate() - Round rate of divider clock
115  * @hw:			handle between common and hardware-specific interfaces
126 	u32 clk_id = divider->clk_id;  in zynqmp_clk_divider_determine_rate()
127 	u32 div_type = divider->div_type;  in zynqmp_clk_divider_determine_rate()
133 	if (divider->flags & CLK_DIVIDER_READ_ONLY) {  in zynqmp_clk_divider_determine_rate()
144 		if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)  in zynqmp_clk_divider_determine_rate()
147 		req->rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, bestdiv);  in zynqmp_clk_divider_determine_rate()
152 	width = fls(divider->max_div);  in zynqmp_clk_divider_determine_rate()
154 	req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate,  in zynqmp_clk_divider_determine_rate()
155 				       NULL, width, divider->flags);  in zynqmp_clk_divider_determine_rate()
157 	if (divider->is_frac && (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) &&  in zynqmp_clk_divider_determine_rate()
158 	    (req->rate % req->best_parent_rate))  in zynqmp_clk_divider_determine_rate()
159 		req->best_parent_rate = req->rate;  in zynqmp_clk_divider_determine_rate()
165  * zynqmp_clk_divider_set_rate() - Set rate of divider clock
166  * @hw:			handle between common and hardware-specific interfaces
177 	u32 clk_id = divider->clk_id;  in zynqmp_clk_divider_set_rate()
178 	u32 div_type = divider->div_type;  in zynqmp_clk_divider_set_rate()
182 	value = zynqmp_divider_get_val(parent_rate, rate, divider->flags);  in zynqmp_clk_divider_set_rate()
191 	if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)  in zynqmp_clk_divider_set_rate()
215  * zynqmp_clk_get_max_divisor() - Get maximum supported divisor from firmware.
266  * zynqmp_clk_register_divider() - Register a divider clock
289 		return ERR_PTR(-ENOMEM);  in zynqmp_clk_register_divider()
292 	if (nodes->type_flag & CLK_DIVIDER_READ_ONLY)  in zynqmp_clk_register_divider()
297 	init.flags = zynqmp_clk_map_common_ccf_flags(nodes->flag);  in zynqmp_clk_register_divider()
303 	div->is_frac = !!((nodes->flag & CLK_FRAC) |  in zynqmp_clk_register_divider()
304 			  (nodes->custom_type_flag & CUSTOM_FLAG_CLK_FRAC));  in zynqmp_clk_register_divider()
305 	div->flags = zynqmp_clk_map_divider_ccf_flags(nodes->type_flag);  in zynqmp_clk_register_divider()
306 	div->hw.init = &init;  in zynqmp_clk_register_divider()
307 	div->clk_id = clk_id;  in zynqmp_clk_register_divider()
308 	div->div_type = nodes->type;  in zynqmp_clk_register_divider()
314 	div->max_div = zynqmp_clk_get_max_divisor(clk_id, nodes->type);  in zynqmp_clk_register_divider()
316 	hw = &div->hw;  in zynqmp_clk_register_divider()