1 // SPDX-License-Identifier: GPL-2.0
3  * Zynq UltraScale+ MPSoC mux
5  *  Copyright (C) 2016-2018 Xilinx
8 #include <linux/clk-provider.h>
10 #include "clk-zynqmp.h"
13  * DOC: basic adjustable multiplexer clock that cannot gate
15  * Traits of this clock:
16  * prepare - clk_prepare only ensures that parents are prepared
17  * enable - clk_enable only ensures that parents are enabled
18  * rate - rate is only affected by parent switching.  No clk_set_rate support
19  * parent - parent is adjustable through clk_set_parent
23  * struct zynqmp_clk_mux - multiplexer clock
25  * @hw:		handle between common and hardware-specific interfaces
26  * @flags:	hardware-specific flags
27  * @clk_id:	Id of clock
38  * zynqmp_clk_mux_get_parent() - Get parent of clock
39  * @hw:		handle between common and hardware-specific interfaces
45 	struct zynqmp_clk_mux *mux = to_zynqmp_clk_mux(hw);  in zynqmp_clk_mux_get_parent()  local
47 	u32 clk_id = mux->clk_id;  in zynqmp_clk_mux_get_parent()
54 		pr_debug("%s() getparent failed for clock: %s, ret = %d\n",  in zynqmp_clk_mux_get_parent()
67  * zynqmp_clk_mux_set_parent() - Set parent of clock
68  * @hw:		handle between common and hardware-specific interfaces
75 	struct zynqmp_clk_mux *mux = to_zynqmp_clk_mux(hw);  in zynqmp_clk_mux_set_parent()  local
77 	u32 clk_id = mux->clk_id;  in zynqmp_clk_mux_set_parent()
83 		pr_debug("%s() set parent failed for clock: %s, ret = %d\n",  in zynqmp_clk_mux_set_parent()
121  * zynqmp_clk_register_mux() - Register a mux table with the clock
123  * @name:		Name of this clock
124  * @clk_id:		Id of this clock
125  * @parents:		Name of this clock's parents
127  * @nodes:		Clock topology node
129  * Return: clock hardware of the registered clock mux
136 	struct zynqmp_clk_mux *mux;  in zynqmp_clk_register_mux()  local
141 	mux = kzalloc(sizeof(*mux), GFP_KERNEL);  in zynqmp_clk_register_mux()
142 	if (!mux)  in zynqmp_clk_register_mux()
143 		return ERR_PTR(-ENOMEM);  in zynqmp_clk_register_mux()
146 	if (nodes->type_flag & CLK_MUX_READ_ONLY)  in zynqmp_clk_register_mux()
151 	init.flags = zynqmp_clk_map_common_ccf_flags(nodes->flag);  in zynqmp_clk_register_mux()
155 	mux->flags = zynqmp_clk_map_mux_ccf_flags(nodes->type_flag);  in zynqmp_clk_register_mux()
156 	mux->hw.init = &init;  in zynqmp_clk_register_mux()
157 	mux->clk_id = clk_id;  in zynqmp_clk_register_mux()
159 	hw = &mux->hw;  in zynqmp_clk_register_mux()
162 		kfree(mux);  in zynqmp_clk_register_mux()