1 // SPDX-License-Identifier: GPL-2.0-only
3  * Zynq PLL driver
10 #include <linux/clk-provider.h>
15  * struct zynq_pll - pll clock
16  * @hw:		Handle between common and hardware-specific interfaces
17  * @pll_ctrl:	PLL control register
18  * @pll_status:	PLL status register
20  * @lockbit:	Indicates the associated PLL_LOCKED bit in the PLL status
45  * zynq_pll_round_rate() - Round a clock frequency
46  * @hw:		Handle between common and hardware-specific interfaces
56 	fbdiv = DIV_ROUND_CLOSEST(req->rate, req->best_parent_rate);  in zynq_pll_determine_rate()
62 	req->rate = req->best_parent_rate * fbdiv;  in zynq_pll_determine_rate()
68  * zynq_pll_recalc_rate() - Recalculate clock frequency
69  * @hw:			Handle between common and hardware-specific interfaces
80 	 * makes probably sense to redundantly save fbdiv in the struct  in zynq_pll_recalc_rate()
83 	fbdiv = (readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >>  in zynq_pll_recalc_rate()
90  * zynq_pll_is_enabled - Check if a clock is enabled
91  * @hw:		Handle between common and hardware-specific interfaces
103 	spin_lock_irqsave(clk->lock, flags);  in zynq_pll_is_enabled()
105 	reg = readl(clk->pll_ctrl);  in zynq_pll_is_enabled()
107 	spin_unlock_irqrestore(clk->lock, flags);  in zynq_pll_is_enabled()
113  * zynq_pll_enable - Enable clock
114  * @hw:		Handle between common and hardware-specific interfaces
126 	pr_info("PLL: enable\n");  in zynq_pll_enable()
128 	/* Power up PLL and wait for lock */  in zynq_pll_enable()
129 	spin_lock_irqsave(clk->lock, flags);  in zynq_pll_enable()
131 	reg = readl(clk->pll_ctrl);  in zynq_pll_enable()
133 	writel(reg, clk->pll_ctrl);  in zynq_pll_enable()
134 	while (!(readl(clk->pll_status) & (1 << clk->lockbit)))  in zynq_pll_enable()
137 	spin_unlock_irqrestore(clk->lock, flags);  in zynq_pll_enable()
143  * zynq_pll_disable - Disable clock
144  * @hw:		Handle between common and hardware-specific interfaces
156 	pr_info("PLL: shutdown\n");  in zynq_pll_disable()
158 	/* shut down PLL */  in zynq_pll_disable()
159 	spin_lock_irqsave(clk->lock, flags);  in zynq_pll_disable()
161 	reg = readl(clk->pll_ctrl);  in zynq_pll_disable()
163 	writel(reg, clk->pll_ctrl);  in zynq_pll_disable()
165 	spin_unlock_irqrestore(clk->lock, flags);  in zynq_pll_disable()
177  * clk_register_zynq_pll() - Register PLL with the clock framework
178  * @name:	PLL name
180  * @pll_ctrl:	Pointer to PLL control register
181  * @pll_status:	Pointer to PLL status register
182  * @lock_index:	Bit index to this PLL's lock status bit in @pll_status
190 	struct zynq_pll *pll;  in clk_register_zynq_pll()  local
203 	pll = kmalloc(sizeof(*pll), GFP_KERNEL);  in clk_register_zynq_pll()
204 	if (!pll)  in clk_register_zynq_pll()
205 		return ERR_PTR(-ENOMEM);  in clk_register_zynq_pll()
208 	pll->hw.init = &initd;  in clk_register_zynq_pll()
209 	pll->pll_ctrl = pll_ctrl;  in clk_register_zynq_pll()
210 	pll->pll_status = pll_status;  in clk_register_zynq_pll()
211 	pll->lockbit = lock_index;  in clk_register_zynq_pll()
212 	pll->lock = lock;  in clk_register_zynq_pll()
214 	spin_lock_irqsave(pll->lock, flags);  in clk_register_zynq_pll()
216 	reg = readl(pll->pll_ctrl);  in clk_register_zynq_pll()
218 	writel(reg, pll->pll_ctrl);  in clk_register_zynq_pll()
220 	spin_unlock_irqrestore(pll->lock, flags);  in clk_register_zynq_pll()
222 	clk = clk_register(NULL, &pll->hw);  in clk_register_zynq_pll()
229 	kfree(pll);  in clk_register_zynq_pll()