Lines Matching refs:CLK_DIVIDER_ALLOW_ZERO
140 CLK_DIVIDER_ALLOW_ZERO, fclk_lock); in zynq_clk_register_fclk()
144 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_register_fclk()
195 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock); in zynq_clk_register_periph_clk()
283 CLK_DIVIDER_ALLOW_ZERO, &armclk_lock); in zynq_clk_setup()
327 CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); in zynq_clk_setup()
333 CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); in zynq_clk_setup()
340 CLK_DIVIDER_ALLOW_ZERO, &dciclk_lock); in zynq_clk_setup()
343 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_setup()
392 CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock); in zynq_clk_setup()
395 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_setup()
417 CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock); in zynq_clk_setup()
420 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_setup()
446 CLK_DIVIDER_ALLOW_ZERO, &canclk_lock); in zynq_clk_setup()
449 CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, in zynq_clk_setup()
486 CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock); in zynq_clk_setup()