Lines Matching refs:divider
114 /* Extract divider instance from clock hardware instance */
148 * struct clk_wzrd_divider - clock divider specific to clk_wzrd
151 * @base: base address of register containing the divider
152 * @offset: offset address of register containing the divider
153 * @shift: shift to the divider bit field
154 * @width: width of the divider bit field
155 * @flags: clk_wzrd divider flags
156 * @table: array of value/divider pairs, last entry should have div = 0
159 * @d: value of the common divider
160 * @o: value of the leaf divider
161 * @o_frac: value of the fractional leaf divider
177 spinlock_t *lock; /* divider lock */
199 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
200 void __iomem *div_addr = divider->base + divider->offset;
224 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
225 void __iomem *div_addr = divider->base + divider->offset;
228 val = readl(div_addr) >> divider->shift;
229 val &= div_mask(divider->width);
231 return divider_recalc_rate(hw, parent_rate, val, divider->table,
232 divider->flags, divider->width);
238 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
239 void __iomem *div_addr = divider->base + divider->offset;
244 spin_lock_irqsave(divider->lock, flags);
264 err = readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET,
272 divider->base + WZRD_DR_INIT_VERSAL_OFFSET);
275 err = readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET,
279 spin_unlock_irqrestore(divider->lock, flags);
286 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
287 void __iomem *div_addr = divider->base + divider->offset;
292 spin_lock_irqsave(divider->lock, flags);
304 err = readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET,
312 divider->base + WZRD_DR_INIT_REG_OFFSET);
314 divider->base + WZRD_DR_INIT_REG_OFFSET);
317 err = readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET,
321 spin_unlock_irqrestore(divider->lock, flags);
342 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
365 divider->m = m;
366 divider->d = d;
367 divider->o = o;
380 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
406 divider->m = m >> 3;
407 divider->m_frac = (m - (divider->m << 3)) * 125;
408 divider->d = d;
409 divider->o = o >> 3;
410 divider->o_frac = (o - (divider->o << 3)) * 125;
417 static int clk_wzrd_reconfig(struct clk_wzrd_divider *divider, void __iomem *div_addr)
423 err = readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,
432 return readl_poll_timeout_atomic(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,
441 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
449 writel(0, divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_4));
451 m = divider->m;
454 regval1 = readl(divider->base + WZRD_CLK_CFG_REG(1,
462 writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,
465 writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,
468 value2 = divider->d;
472 writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,
475 writel(regval1, divider->base + WZRD_CLK_CFG_REG(1, WZRD_DIVCLK));
477 value = divider->o;
479 regval1 = readl(divider->base + WZRD_CLK_CFG_REG(1,
493 writel(regval1, divider->base + WZRD_CLK_CFG_REG(1,
496 writel(regval, divider->base + WZRD_CLK_CFG_REG(1,
498 div_addr = divider->base + WZRD_DR_INIT_VERSAL_OFFSET;
500 return clk_wzrd_reconfig(divider, div_addr);
506 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
515 reg = FIELD_PREP(WZRD_CLKOUT_DIVIDE_MASK, divider->o) |
516 FIELD_PREP(WZRD_CLKOUT0_FRAC_MASK, divider->o_frac);
518 writel(reg, divider->base + WZRD_CLK_CFG_REG(0, 2));
519 reg = FIELD_PREP(WZRD_CLKFBOUT_MULT_MASK, divider->m) |
520 FIELD_PREP(WZRD_CLKFBOUT_MULT_FRAC_MASK, divider->m_frac) |
521 FIELD_PREP(WZRD_DIVCLK_DIVIDE_MASK, divider->d);
522 writel(reg, divider->base + WZRD_CLK_CFG_REG(0, 0));
523 writel(0, divider->base + WZRD_CLK_CFG_REG(0, 3));
524 div_addr = divider->base + WZRD_DR_INIT_REG_OFFSET;
525 return clk_wzrd_reconfig(divider, div_addr);
531 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
535 spin_lock_irqsave(divider->lock, flags);
539 spin_unlock_irqrestore(divider->lock, flags);
547 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
551 spin_lock_irqsave(divider->lock, flags);
555 spin_unlock_irqrestore(divider->lock, flags);
563 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
567 reg = readl(divider->base + WZRD_CLK_CFG_REG(0, 0));
571 reg = readl(divider->base + WZRD_CLK_CFG_REG(0, 2));
582 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
586 edge = !!(readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_1)) &
589 reg = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_2));
597 regl = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_4)) &
600 regl = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKFBOUT_3))
609 reg = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKOUT0_1));
614 reg = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_CLKOUT0_2));
629 edged = !!(readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_DESKEW_2)) &
631 reg = readl(divider->base + WZRD_CLK_CFG_REG(1, WZRD_DIVCLK));
641 return divider_recalc_rate(hw, parent_rate, div, divider->table,
642 divider->flags, divider->width);
648 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
656 m = divider->m;
657 d = divider->d;
658 o = divider->o;
660 rate = div_u64(*prate * (m * 1000 + divider->m_frac), d * (o * 1000 + divider->o_frac));
667 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
676 m = divider->m;
677 d = divider->d;
678 o = divider->o;
681 int_freq = divider_recalc_rate(hw, *prate * m, div, divider->table,
682 divider->flags, divider->width);
720 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
721 void __iomem *div_addr = divider->base + divider->offset;
724 div = val & div_mask(divider->width);
736 struct clk_wzrd_divider *divider = to_clk_wzrd_divider(hw);
737 void __iomem *div_addr = divider->base + divider->offset;
754 err = readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,
762 divider->base + WZRD_DR_INIT_REG_OFFSET);
764 divider->base + WZRD_DR_INIT_REG_OFFSET);
767 return readl_poll_timeout(divider->base + WZRD_DR_STATUS_REG_OFFSET, value,
1096 dev_err(dev, "unable to register divider clock\n");
1136 dev_err(dev, "unable to register divider clock\n");