Lines Matching +full:0 +full:x128
35 { TMPV770X_CLK_PIPLL1_DIV4, "pipll1_div4", "pipll1", 0, 1, 4, },
37 { TMPV770X_CLK_PIPLL1_DIV2, "pipll1_div2", "pipll1", 0, 1, 2, },
39 { TMPV770X_CLK_PIPLL1_DIV1, "pipll1_div1", "pipll1", 0, 1, 1, },
42 { TMPV770X_CLK_PIDNNPLL_DIV1, "pidnnpll_div1", "pidnnpll", 0, 1, 1, },
43 { TMPV770X_CLK_PIREFCLK, "pirefclk", "osc2-clk", 0, 1, 1, },
44 { TMPV770X_CLK_WDTCLK, "wdtclk", "osc2-clk", 0, 1, 1, },
51 CLK_SET_RATE_PARENT, 0x34, 0x134, 4, 200,
55 CLK_SET_RATE_PARENT, 0x34, 0x134, 5, 20,
59 CLK_SET_RATE_PARENT, 0x34, 0x134, 6, 10,
63 CLK_SET_RATE_PARENT, 0x34, 0x134, 7, 4,
70 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x4c, 0x14c, 0, 1,
74 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x38, 0x138, 0, 1,
78 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x38, 0x138, 1, 24,
82 CLK_IGNORE_UNUSED, 0x8, 0x108, 0, 2, //FIX!!
86 0, 0x34, 0x134, 0, 2,
90 0, 0x28, 0x128, 0, 2,
94 0, 0x28, 0x128, 1, 2,
98 0, 0x28, 0x128, 2, 2,
102 0, 0x28, 0x128, 3, 2,
106 0, 0x28, 0x128, 4, 2,
110 0, 0x28, 0x128, 5, 2,
114 0, 0x28, 0x128, 6, 2,
118 //CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2c, 0x12c, 0, 4,
119 0, 0x2c, 0x12c, 0, 4,
123 //CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0x2c, 0x12c, 1, 4,
124 0, 0x2c, 0x12c, 1, 4,
128 0, 0x2c, 0x12c, 2, 4,
132 0, 0x2c, 0x12c, 3, 4,
136 0, 0x30, 0x130, 0, 4,
140 0, 0x30, 0x130, 1, 4,
144 0, 0x30, 0x130, 2, 4,
148 0, 0x30, 0x130, 3, 4,
152 0, 0x30, 0x130, 4, 4,
156 0, 0x30, 0x130, 5, 4,
160 0, 0x30, 0x130, 6, 4,
164 0, 0x30, 0x130, 7, 4,
168 0, 0x30, 0x130, 8, 4,
173 0, 0x64, 0x164, 0, 4,
178 0, 0x68, 0x168, 9, 32,
182 0, 0x10, 0x110, 8, 4,
186 0, 0x14, 0x114, 0, 4,
191 [TMPV770X_RESET_PIETHER_2P5M] = { 0x434, 0x534, 4, },
192 [TMPV770X_RESET_PIETHER_25M] = { 0x434, 0x534, 5, },
193 [TMPV770X_RESET_PIETHER_50M] = { 0x434, 0x534, 6, },
194 [TMPV770X_RESET_PIETHER_125M] = { 0x434, 0x534, 7, },
195 [TMPV770X_RESET_HOX] = { 0x44c, 0x54c, 0, },
196 [TMPV770X_RESET_PCIE_MSTR] = { 0x438, 0x538, 0, },
197 [TMPV770X_RESET_PCIE_AUX] = { 0x438, 0x538, 1, },
198 [TMPV770X_RESET_PIINTC] = { 0x408, 0x508, 0, },
199 [TMPV770X_RESET_PIETHER_BUS] = { 0x434, 0x534, 0, },
200 [TMPV770X_RESET_PISPI0] = { 0x428, 0x528, 0, },
201 [TMPV770X_RESET_PISPI1] = { 0x428, 0x528, 1, },
202 [TMPV770X_RESET_PISPI2] = { 0x428, 0x528, 2, },
203 [TMPV770X_RESET_PISPI3] = { 0x428, 0x528, 3, },
204 [TMPV770X_RESET_PISPI4] = { 0x428, 0x528, 4, },
205 [TMPV770X_RESET_PISPI5] = { 0x428, 0x528, 5, },
206 [TMPV770X_RESET_PISPI6] = { 0x428, 0x528, 6, },
207 [TMPV770X_RESET_PIUART0] = { 0x42c, 0x52c, 0, },
208 [TMPV770X_RESET_PIUART1] = { 0x42c, 0x52c, 1, },
209 [TMPV770X_RESET_PIUART2] = { 0x42c, 0x52c, 2, },
210 [TMPV770X_RESET_PIUART3] = { 0x42c, 0x52c, 3, },
211 [TMPV770X_RESET_PII2C0] = { 0x430, 0x530, 0, },
212 [TMPV770X_RESET_PII2C1] = { 0x430, 0x530, 1, },
213 [TMPV770X_RESET_PII2C2] = { 0x430, 0x530, 2, },
214 [TMPV770X_RESET_PII2C3] = { 0x430, 0x530, 3, },
215 [TMPV770X_RESET_PII2C4] = { 0x430, 0x530, 4, },
216 [TMPV770X_RESET_PII2C5] = { 0x430, 0x530, 5, },
217 [TMPV770X_RESET_PII2C6] = { 0x430, 0x530, 6, },
218 [TMPV770X_RESET_PII2C7] = { 0x430, 0x530, 7, },
219 [TMPV770X_RESET_PII2C8] = { 0x430, 0x530, 8, },
220 [TMPV770X_RESET_PIPCMIF] = { 0x464, 0x564, 0, },
221 [TMPV770X_RESET_PICKMON] = { 0x410, 0x510, 8, },
222 [TMPV770X_RESET_SBUSCLK] = { 0x414, 0x514, 0, },
250 for (i = 0; i < (ARRAY_SIZE(fixed_clk_tables)); i++) in visconti_clk_probe()