74 	 * bits of the v PLL divider. Bit 8 is tied low and always zero,  in vco_get()
75 	 * r is hardwired to 22 and output divider s is hardwired to 1  in vco_get()
81 		vco->v = val & INTEGRATOR_AP_CM_BITS;  in vco_get()
82 		vco->r = 22;  in vco_get()
89 	 * access the low eight bits of the v PLL divider. Bit 8 is tied low  in vco_get()
96 		vco->v = val & INTEGRATOR_AP_SYS_BITS;  in vco_get()
106 	 * bit to 0 yields v = 17, r = 22 and OD = 1, whereas setting the  in vco_get()
107 	 * bit to 1 yields v = 14, r = 14 and OD = 1 giving the frequencies  in vco_get()
113 		vco->v = divxy ? 17 : 14;  in vco_get()
114 		vco->r = divxy ? 22 : 14;  in vco_get()
121 	 * of the v PLL divider. Bit 8 is tied low and always zero,  in vco_get()
122 	 * r is hardwired to 22 and the output divider s is accessible  in vco_get()
128 		vco->v = val & 0xFF;  in vco_get()
129 		vco->r = 22;  in vco_get()
135 		vco->v = (val >> 12) & 0xFF;  in vco_get()
136 		vco->r = 22;  in vco_get()
141 	vco->v = val & 0x1ff;  in vco_get()
162 		val = vco.v & 0xFF;  in vco_set()
163 		if (vco.v & 0x100)  in vco_set()
167 		if (vco.r != 22)  in vco_set()
168 			pr_err("ICST error: tried to use RDW != 22\n");  in vco_set()
172 		val = vco.v & 0xFF;  in vco_set()
173 		if (vco.v & 0x100)  in vco_set()
178 			pr_err("ICST error: tried to use RDW != 22\n");  in vco_set()
182 		val = (vco.v & 0xFF) | vco.s << 8;  in vco_set()
183 		if (vco.v & 0x100)  in vco_set()
185 		if (vco.r != 22)  in vco_set()
186 			pr_err("ICST error: tried to use RDW != 22\n");  in vco_set()
190 		val = ((vco.v & 0xFF) << 12) | (vco.s << 20);  in vco_set()
191 		if (vco.v & 0x100)  in vco_set()
193 		if (vco.r != 22)  in vco_set()
194 			pr_err("ICST error: tried to use RDW != 22\n");  in vco_set()
199 		val = vco.v | (vco.r << 9) | (vco.s << 16);  in vco_set()
447 	/* r is hardcoded to 22 and this is the actual divisor, +2 */
475 	/* r is hardcoded to 14 or 22 and this is the actual divisors +2 */