1 // SPDX-License-Identifier: GPL-2.0-only
7  * Tero Kristo <t-kristo@ti.com>
11 #include <linux/clk-provider.h>
137  * _register_dpll - low level registration of a DPLL clock
141  * Finalizes DPLL registration process. In case a failure (clk-ref or
142  * clk-bypass is missing), the clock is added to retry list and
150 	struct dpll_data *dd = clk_hw->dpll_data;  in _register_dpll()
153 	const struct clk_init_data *init = hw->init;  in _register_dpll()
157 		pr_debug("clk-ref missing for %pOFn, retry later\n",  in _register_dpll()
165 	dd->clk_ref = __clk_get_hw(clk);  in _register_dpll()
170 		pr_debug("clk-bypass missing for %pOFn, retry later\n",  in _register_dpll()
178 	dd->clk_bypass = __clk_get_hw(clk);  in _register_dpll()
182 	clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name);  in _register_dpll()
186 		kfree(init->parent_names);  in _register_dpll()
192 	kfree(clk_hw->dpll_data);  in _register_dpll()
193 	kfree(init->parent_names);  in _register_dpll()
202  * _register_dpll_x2 - Registers a DPLLx2 clock
229 	clk_hw->ops = hw_ops;  in _register_dpll_x2()
230 	clk_hw->hw.init = &init;  in _register_dpll_x2()
242 		/* Check if register defined, if not, drop hw-ops */  in _register_dpll_x2()
245 			clk_hw->ops = NULL;  in _register_dpll_x2()
246 		} else if (ti_clk_get_reg_addr(node, 0, &clk_hw->clksel_reg)) {  in _register_dpll_x2()
254 	clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name);  in _register_dpll_x2()
264  * of_ti_dpll_setup - Setup function for OMAP DPLL clocks
289 	clk_hw->dpll_data = dd;  in of_ti_dpll_setup()
290 	clk_hw->ops = &clkhwops_omap3_dpll;  in of_ti_dpll_setup()
291 	clk_hw->hw.init = init;  in of_ti_dpll_setup()
293 	init->name = ti_dt_clk_name(node);  in of_ti_dpll_setup()
294 	init->ops = ops;  in of_ti_dpll_setup()
296 	init->num_parents = of_clk_get_parent_count(node);  in of_ti_dpll_setup()
297 	if (!init->num_parents) {  in of_ti_dpll_setup()
302 	parent_names = kcalloc(init->num_parents, sizeof(char *), GFP_KERNEL);  in of_ti_dpll_setup()
306 	of_clk_parent_fill(node, parent_names, init->num_parents);  in of_ti_dpll_setup()
308 	init->parent_names = parent_names;  in of_ti_dpll_setup()
310 	if (ti_clk_get_reg_addr(node, 0, &dd->control_reg))  in of_ti_dpll_setup()
318 	if (!dd->idlest_mask) {  in of_ti_dpll_setup()
319 		if (ti_clk_get_reg_addr(node, 1, &dd->mult_div1_reg))  in of_ti_dpll_setup()
322 		clk_hw->ops = &clkhwops_omap2xxx_dpll;  in of_ti_dpll_setup()
323 		omap2xxx_clkt_dpllcore_init(&clk_hw->hw);  in of_ti_dpll_setup()
326 		if (ti_clk_get_reg_addr(node, 1, &dd->idlest_reg))  in of_ti_dpll_setup()
329 		if (ti_clk_get_reg_addr(node, 2, &dd->mult_div1_reg))  in of_ti_dpll_setup()
333 	if (dd->autoidle_mask) {  in of_ti_dpll_setup()
334 		if (ti_clk_get_reg_addr(node, 3, &dd->autoidle_reg))  in of_ti_dpll_setup()
342 	if (dd->ssc_deltam_int_mask && dd->ssc_deltam_frac_mask &&  in of_ti_dpll_setup()
343 	    dd->ssc_modfreq_mant_mask && dd->ssc_modfreq_exp_mask) {  in of_ti_dpll_setup()
345 					&dd->ssc_deltam_reg))  in of_ti_dpll_setup()
349 					&dd->ssc_modfreq_reg))  in of_ti_dpll_setup()
352 		of_property_read_u32(node, "ti,ssc-modfreq-hz",  in of_ti_dpll_setup()
353 				     &dd->ssc_modfreq);  in of_ti_dpll_setup()
354 		of_property_read_u32(node, "ti,ssc-deltam", &dd->ssc_deltam);  in of_ti_dpll_setup()
355 		dd->ssc_downspread =  in of_ti_dpll_setup()
356 			of_property_read_bool(node, "ti,ssc-downspread");  in of_ti_dpll_setup()
359 	if (of_property_read_bool(node, "ti,low-power-stop"))  in of_ti_dpll_setup()
362 	if (of_property_read_bool(node, "ti,low-power-bypass"))  in of_ti_dpll_setup()
368 	if (!of_property_read_u32(node, "ti,min-div", &min_div) &&  in of_ti_dpll_setup()
369 	    min_div > dd->min_divider)  in of_ti_dpll_setup()
370 		dd->min_divider = min_div;  in of_ti_dpll_setup()
373 		dd->modes = dpll_mode;  in of_ti_dpll_setup()
375 	_register_dpll(&clk_hw->hw, node);  in of_ti_dpll_setup()
391 CLK_OF_DECLARE(ti_omap4_dpll_x2_clock, "ti,omap4-dpll-x2-clock",
400 CLK_OF_DECLARE(ti_am3_dpll_x2_clock, "ti,am3-dpll-x2-clock",
427 CLK_OF_DECLARE(ti_omap3_dpll_clock, "ti,omap3-dpll-clock",
446 CLK_OF_DECLARE(ti_omap3_core_dpll_clock, "ti,omap3-dpll-core-clock",
466 CLK_OF_DECLARE(ti_omap3_per_dpll_clock, "ti,omap3-dpll-per-clock",
488 CLK_OF_DECLARE(ti_omap3_per_jtype_dpll_clock, "ti,omap3-dpll-per-j-type-clock",
508 CLK_OF_DECLARE(ti_omap4_dpll_clock, "ti,omap4-dpll-clock",
529 CLK_OF_DECLARE(of_ti_omap5_mpu_dpll_clock, "ti,omap5-mpu-dpll-clock",
548 CLK_OF_DECLARE(ti_omap4_core_dpll_clock, "ti,omap4-dpll-core-clock",
571 CLK_OF_DECLARE(ti_omap4_m4xen_dpll_clock, "ti,omap4-dpll-m4xen-clock",
592 CLK_OF_DECLARE(ti_omap4_jtype_dpll_clock, "ti,omap4-dpll-j-type-clock",
618 CLK_OF_DECLARE(ti_am3_no_gate_dpll_clock, "ti,am3-dpll-no-gate-clock",
638 CLK_OF_DECLARE(ti_am3_jtype_dpll_clock, "ti,am3-dpll-j-type-clock",
659 	       "ti,am3-dpll-no-gate-j-type-clock",
684 CLK_OF_DECLARE(ti_am3_dpll_clock, "ti,am3-dpll-clock", of_ti_am3_dpll_setup);
702 CLK_OF_DECLARE(ti_am3_core_dpll_clock, "ti,am3-dpll-core-clock",
717 CLK_OF_DECLARE(ti_omap2_core_dpll_clock, "ti,omap2-dpll-core-clock",