1 // SPDX-License-Identifier: GPL-2.0-only
7  * J Keerthy <j-keerthy@ti.com>
11 #include <linux/clk-provider.h>
41 	ad = clk->dpll_data;  in dra7_apll_enable()
43 		return -EINVAL;  in dra7_apll_enable()
45 	clk_name = clk_hw_get_name(&clk->hw);  in dra7_apll_enable()
47 	state <<= __ffs(ad->idlest_mask);  in dra7_apll_enable()
49 	/* Check is already locked */  in dra7_apll_enable()
50 	v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg);  in dra7_apll_enable()
52 	if ((v & ad->idlest_mask) == state)  in dra7_apll_enable()
55 	v = ti_clk_ll_ops->clk_readl(&ad->control_reg);  in dra7_apll_enable()
56 	v &= ~ad->enable_mask;  in dra7_apll_enable()
57 	v |= APLL_FORCE_LOCK << __ffs(ad->enable_mask);  in dra7_apll_enable()
58 	ti_clk_ll_ops->clk_writel(v, &ad->control_reg);  in dra7_apll_enable()
60 	state <<= __ffs(ad->idlest_mask);  in dra7_apll_enable()
63 		v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg);  in dra7_apll_enable()
64 		if ((v & ad->idlest_mask) == state)  in dra7_apll_enable()
74 			clk_name, (state) ? "locked" : "bypassed");  in dra7_apll_enable()
75 		r = -EBUSY;  in dra7_apll_enable()
78 			 clk_name, (state) ? "locked" : "bypassed", i);  in dra7_apll_enable()
90 	ad = clk->dpll_data;  in dra7_apll_disable()
92 	state <<= __ffs(ad->idlest_mask);  in dra7_apll_disable()
94 	v = ti_clk_ll_ops->clk_readl(&ad->control_reg);  in dra7_apll_disable()
95 	v &= ~ad->enable_mask;  in dra7_apll_disable()
96 	v |= APLL_AUTO_IDLE << __ffs(ad->enable_mask);  in dra7_apll_disable()
97 	ti_clk_ll_ops->clk_writel(v, &ad->control_reg);  in dra7_apll_disable()
106 	ad = clk->dpll_data;  in dra7_apll_is_enabled()
108 	v = ti_clk_ll_ops->clk_readl(&ad->control_reg);  in dra7_apll_is_enabled()
109 	v &= ad->enable_mask;  in dra7_apll_is_enabled()
111 	v >>= __ffs(ad->enable_mask);  in dra7_apll_is_enabled()
133 	struct dpll_data *ad = clk_hw->dpll_data;  in omap_clk_register_apll()
136 	const struct clk_init_data *init = clk_hw->hw.init;  in omap_clk_register_apll()
140 		pr_debug("clk-ref for %pOFn not ready, retry\n",  in omap_clk_register_apll()
148 	ad->clk_ref = __clk_get_hw(clk);  in omap_clk_register_apll()
152 		pr_debug("clk-bypass for %pOFn not ready, retry\n",  in omap_clk_register_apll()
160 	ad->clk_bypass = __clk_get_hw(clk);  in omap_clk_register_apll()
163 	clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name);  in omap_clk_register_apll()
166 		kfree(init->parent_names);  in omap_clk_register_apll()
172 	kfree(clk_hw->dpll_data);  in omap_clk_register_apll()
173 	kfree(init->parent_names);  in omap_clk_register_apll()
192 	clk_hw->dpll_data = ad;  in of_dra7_apll_setup()
193 	clk_hw->hw.init = init;  in of_dra7_apll_setup()
195 	init->name = ti_dt_clk_name(node);  in of_dra7_apll_setup()
196 	init->ops = &apll_ck_ops;  in of_dra7_apll_setup()
198 	init->num_parents = of_clk_get_parent_count(node);  in of_dra7_apll_setup()
199 	if (init->num_parents < 1) {  in of_dra7_apll_setup()
200 		pr_err("dra7 apll %pOFn must have parent(s)\n", node);  in of_dra7_apll_setup()
204 	parent_names = kcalloc(init->num_parents, sizeof(char *), GFP_KERNEL);  in of_dra7_apll_setup()
208 	of_clk_parent_fill(node, parent_names, init->num_parents);  in of_dra7_apll_setup()
210 	init->parent_names = parent_names;  in of_dra7_apll_setup()
212 	ret = ti_clk_get_reg_addr(node, 0, &ad->control_reg);  in of_dra7_apll_setup()
213 	ret |= ti_clk_get_reg_addr(node, 1, &ad->idlest_reg);  in of_dra7_apll_setup()
218 	ad->idlest_mask = 0x1;  in of_dra7_apll_setup()
219 	ad->enable_mask = 0x3;  in of_dra7_apll_setup()
221 	omap_clk_register_apll(&clk_hw->hw, node);  in of_dra7_apll_setup()
230 CLK_OF_DECLARE(dra7_apll_clock, "ti,dra7-apll-clock", of_dra7_apll_setup);
238 	struct dpll_data *ad = clk->dpll_data;  in omap2_apll_is_enabled()
241 	v = ti_clk_ll_ops->clk_readl(&ad->control_reg);  in omap2_apll_is_enabled()
242 	v &= ad->enable_mask;  in omap2_apll_is_enabled()
244 	v >>= __ffs(ad->enable_mask);  in omap2_apll_is_enabled()
255 		return clk->fixed_rate;  in omap2_apll_recalc()
263 	struct dpll_data *ad = clk->dpll_data;  in omap2_apll_enable()
267 	v = ti_clk_ll_ops->clk_readl(&ad->control_reg);  in omap2_apll_enable()
268 	v &= ~ad->enable_mask;  in omap2_apll_enable()
269 	v |= OMAP2_EN_APLL_LOCKED << __ffs(ad->enable_mask);  in omap2_apll_enable()
270 	ti_clk_ll_ops->clk_writel(v, &ad->control_reg);  in omap2_apll_enable()
273 		v = ti_clk_ll_ops->clk_readl(&ad->idlest_reg);  in omap2_apll_enable()
274 		if (v & ad->idlest_mask)  in omap2_apll_enable()
283 		pr_warn("%s failed to transition to locked\n",  in omap2_apll_enable()
284 			clk_hw_get_name(&clk->hw));  in omap2_apll_enable()
285 		return -EBUSY;  in omap2_apll_enable()
294 	struct dpll_data *ad = clk->dpll_data;  in omap2_apll_disable()
297 	v = ti_clk_ll_ops->clk_readl(&ad->control_reg);  in omap2_apll_disable()
298 	v &= ~ad->enable_mask;  in omap2_apll_disable()
299 	v |= OMAP2_EN_APLL_STOPPED << __ffs(ad->enable_mask);  in omap2_apll_disable()
300 	ti_clk_ll_ops->clk_writel(v, &ad->control_reg);  in omap2_apll_disable()
312 	struct dpll_data *ad = clk->dpll_data;  in omap2_apll_set_autoidle()
315 	v = ti_clk_ll_ops->clk_readl(&ad->autoidle_reg);  in omap2_apll_set_autoidle()
316 	v &= ~ad->autoidle_mask;  in omap2_apll_set_autoidle()
317 	v |= val << __ffs(ad->autoidle_mask);  in omap2_apll_set_autoidle()
318 	ti_clk_ll_ops->clk_writel(v, &ad->control_reg);  in omap2_apll_set_autoidle()
357 	clk_hw->dpll_data = ad;  in of_omap2_apll_setup()
358 	clk_hw->hw.init = init;  in of_omap2_apll_setup()
359 	init->ops = &omap2_apll_ops;  in of_omap2_apll_setup()
361 	init->name = name;  in of_omap2_apll_setup()
362 	clk_hw->ops = &omap2_apll_hwops;  in of_omap2_apll_setup()
364 	init->num_parents = of_clk_get_parent_count(node);  in of_omap2_apll_setup()
365 	if (init->num_parents != 1) {  in of_omap2_apll_setup()
366 		pr_err("%pOFn must have one parent\n", node);  in of_omap2_apll_setup()
371 	init->parent_names = &parent_name;  in of_omap2_apll_setup()
373 	if (of_property_read_u32(node, "ti,clock-frequency", &val)) {  in of_omap2_apll_setup()
374 		pr_err("%pOFn missing clock-frequency\n", node);  in of_omap2_apll_setup()
377 	clk_hw->fixed_rate = val;  in of_omap2_apll_setup()
379 	clk_hw->enable_bit = ti_clk_get_legacy_bit_shift(node);  in of_omap2_apll_setup()
380 	ad->enable_mask = 0x3 << clk_hw->enable_bit;  in of_omap2_apll_setup()
381 	ad->autoidle_mask = 0x3 << clk_hw->enable_bit;  in of_omap2_apll_setup()
383 	if (of_property_read_u32(node, "ti,idlest-shift", &val)) {  in of_omap2_apll_setup()
384 		pr_err("%pOFn missing idlest-shift\n", node);  in of_omap2_apll_setup()
388 	ad->idlest_mask = 1 << val;  in of_omap2_apll_setup()
390 	ret = ti_clk_get_reg_addr(node, 0, &ad->control_reg);  in of_omap2_apll_setup()
391 	ret |= ti_clk_get_reg_addr(node, 1, &ad->autoidle_reg);  in of_omap2_apll_setup()
392 	ret |= ti_clk_get_reg_addr(node, 2, &ad->idlest_reg);  in of_omap2_apll_setup()
398 	clk = of_ti_clk_register_omap_hw(node, &clk_hw->hw, name);  in of_omap2_apll_setup()
409 CLK_OF_DECLARE(omap2_apll_clock, "ti,omap2-apll-clock",