Lines Matching full:common
52 struct ccu_common common;
59 struct ccu_common common;
63 struct ccu_common common;
93 .common = { \
111 struct ccu_common *common = hw_to_ccu_common(hw);
113 return container_of(common, struct ccu_pll, common);
118 struct ccu_common *common = hw_to_ccu_common(hw);
120 return container_of(common, struct ccu_div, common);
125 struct ccu_common *common = hw_to_ccu_common(hw);
127 return container_of(common, struct ccu_gate, common);
130 static u8 ccu_get_parent_helper(struct ccu_common *common,
136 regmap_read(common->map, common->cfg0, &val);
143 static int ccu_set_parent_helper(struct ccu_common *common,
147 return regmap_update_bits(common->map, common->cfg0,
152 static void ccu_disable_helper(struct ccu_common *common, u32 gate)
156 regmap_update_bits(common->map, common->cfg0,
160 static int ccu_enable_helper(struct ccu_common *common, u32 gate)
168 ret = regmap_update_bits(common->map, common->cfg0, gate, gate);
169 regmap_read(common->map, common->cfg0, &val);
173 static int ccu_is_enabled_helper(struct ccu_common *common, u32 gate)
180 regmap_read(common->map, common->cfg0, &val);
191 regmap_read(cd->common.map, cd->common.cfg0, &val);
204 return ccu_get_parent_helper(&cd->common, &cd->mux);
211 return ccu_set_parent_helper(&cd->common, &cd->mux, index);
218 ccu_disable_helper(&cd->common, cd->enable);
225 return ccu_enable_helper(&cd->common, cd->enable);
232 return ccu_is_enabled_helper(&cd->common, cd->enable);
253 regmap_read(pll->common.map, pll->common.cfg0, &cfg0);
254 regmap_read(pll->common.map, pll->common.cfg1, &cfg1);
276 regmap_read(pll->common.map, pll->common.cfg0, &cfg0);
277 regmap_read(pll->common.map, pll->common.cfg1, &cfg1);
310 .common = {
322 .common = {
334 .common = {
346 &gmac_pll_clk.common.hw
350 { .hw = &gmac_pll_clk.common.hw }
354 .common = {
366 &video_pll_clk.common.hw
370 { .hw = &video_pll_clk.common.hw }
374 .common = {
386 &dpu0_pll_clk.common.hw
390 .common = {
402 &dpu1_pll_clk.common.hw
406 .common = {
418 { .hw = &cpu_pll0_clk.common.hw },
430 { .hw = &cpu_pll1_clk.common.hw }
440 { .hw = &gmac_pll_clk.common.hw },
447 .common = {
458 { .hw = &ahb2_cpusys_hclk.common.hw }
462 &ahb2_cpusys_hclk.common.hw,
467 .common = {
478 { .hw = &apb3_cpusys_pclk.common.hw }
483 .common = {
494 { .hw = &axi4_cpusys2_aclk.common.hw }
498 { .hw = &video_pll_clk.common.hw },
505 .common = {
516 { .hw = &axi_aclk.common.hw }
520 { .hw = &gmac_pll_clk.common.hw },
528 .common = {
539 { .hw = &perisys_ahb_hclk.common.hw }
543 &perisys_ahb_hclk.common.hw
548 .common = {
559 { .hw = &perisys_apb_pclk.common.hw }
564 .common = {
575 { .hw = &peri2sys_apb_pclk.common.hw }
593 .common = {
607 .common = {
621 .common = {
635 .common = {
646 { .hw = &gmac_pll_clk.common.hw },
654 .common = {
665 &gmac_pll_clk.common.hw,
666 &video_pll_clk.common.hw
673 .common = {
685 .common = {
697 .common = {
710 .common = {
722 .common = {
735 .common = {
748 .common = {
760 .common = {
772 .common = {
783 &video_pll_clk.common.hw, 4, 1, 0);
913 &gmac_pll_clk.common.hw, 10, 1, 0);
927 &cpu_pll0_clk.common,
928 &cpu_pll1_clk.common,
929 &gmac_pll_clk.common,
930 &video_pll_clk.common,
931 &dpu0_pll_clk.common,
932 &dpu1_pll_clk.common,
933 &tee_pll_clk.common,
937 &ahb2_cpusys_hclk.common,
938 &apb3_cpusys_pclk.common,
939 &axi4_cpusys2_aclk.common,
940 &perisys_ahb_hclk.common,
941 &perisys_apb_pclk.common,
942 &axi_aclk.common,
943 &peri2sys_apb_pclk.common,
944 &out1_clk.common,
945 &out2_clk.common,
946 &out3_clk.common,
947 &out4_clk.common,
948 &apb_pclk.common,
949 &npu_clk.common,
950 &vi_clk.common,
951 &vi_ahb_clk.common,
952 &vo_axi_clk.common,
953 &vp_apb_clk.common,
954 &vp_axi_clk.common,
955 &venc_clk.common,
956 &dpu0_clk.common,
957 &dpu1_clk.common,
967 &emmc_sdio_clk.common,
968 &aon2cpu_a2x_clk.common,
969 &x2x_cpusys_clk.common,
970 &brom_clk.common,
971 &bmu_clk.common,
972 &cpu2aon_x2h_clk.common,
973 &cpu2peri_x2h_clk.common,
974 &cpu2vp_clk.common,
975 &perisys_apb1_hclk.common,
976 &perisys_apb2_hclk.common,
977 &perisys_apb3_hclk.common,
978 &perisys_apb4_hclk.common,
979 &npu_axi_clk.common,
980 &gmac1_clk.common,
981 &padctrl1_clk.common,
982 &dsmart_clk.common,
983 &padctrl0_clk.common,
984 &gmac_axi_clk.common,
985 &gpio3_clk.common,
986 &gmac0_clk.common,
987 &pwm_clk.common,
988 &qspi0_clk.common,
989 &qspi1_clk.common,
990 &spi_clk.common,
991 &uart0_pclk.common,
992 &uart1_pclk.common,
993 &uart2_pclk.common,
994 &uart3_pclk.common,
995 &uart4_pclk.common,
996 &uart5_pclk.common,
997 &gpio0_clk.common,
998 &gpio1_clk.common,
999 &gpio2_clk.common,
1000 &i2c0_clk.common,
1001 &i2c1_clk.common,
1002 &i2c2_clk.common,
1003 &i2c3_clk.common,
1004 &i2c4_clk.common,
1005 &i2c5_clk.common,
1006 &spinlock_clk.common,
1007 &dma_clk.common,
1008 &mbox0_clk.common,
1009 &mbox1_clk.common,
1010 &mbox2_clk.common,
1011 &mbox3_clk.common,
1012 &wdt0_clk.common,
1013 &wdt1_clk.common,
1014 &timer0_clk.common,
1015 &timer1_clk.common,
1016 &sram0_clk.common,
1017 &sram1_clk.common,
1018 &sram2_clk.common,
1019 &sram3_clk.common,
1023 &axi4_vo_aclk.common,
1024 &gpu_core_clk.common,
1025 &gpu_cfg_aclk.common,
1026 &dpu0_pixelclk.common,
1027 &dpu1_pixelclk.common,
1028 &dpu_hclk.common,
1029 &dpu_aclk.common,
1030 &dpu_cclk.common,
1031 &hdmi_sfr_clk.common,
1032 &hdmi_pclk.common,
1033 &hdmi_cec_clk.common,
1034 &mipi_dsi0_pclk.common,
1035 &mipi_dsi1_pclk.common,
1036 &mipi_dsi0_cfg_clk.common,
1037 &mipi_dsi1_cfg_clk.common,
1038 &mipi_dsi0_refclk.common,
1039 &mipi_dsi1_refclk.common,
1040 &hdmi_i2s_clk.common,
1041 &x2h_dpu1_aclk.common,
1042 &x2h_dpu_aclk.common,
1043 &axi4_vo_pclk.common,
1044 &iopmp_vosys_dpu_pclk.common,
1045 &iopmp_vosys_dpu1_pclk.common,
1046 &iopmp_vosys_gpu_pclk.common,
1047 &iopmp_dpu1_aclk.common,
1048 &iopmp_dpu_aclk.common,
1049 &iopmp_gpu_aclk.common,
1050 &mipi_dsi0_pixclk.common,
1051 &mipi_dsi1_pixclk.common,
1052 &hdmi_pixclk.common
1136 priv->hws[cp->common.clkid] = &cp->common.hw;
1148 priv->hws[cd->common.clkid] = &cd->common.hw;
1169 cg->common.hw.init->name,
1170 cg->common.hw.init->parent_data,
1171 cg->common.hw.init->flags,
1172 base + cg->common.cfg0,
1177 priv->hws[cg->common.clkid] = hw;