Lines Matching +full:pll +full:- +full:periph
1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
99 * @flags: hardware-specific flags
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
107 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
108 * flag indicates that this divider is for fixed rate PLL.
109 * TEGRA_DIVIDER_INT - Some modules can not cope with the duty cycle when
112 * TEGRA_DIVIDER_UART - UART module divider has additional enable bit which is
142 * Tegra PLL:
144 * In general, there are 3 requirements for each PLL
150 * The final PLL output frequency (FO) = VCO >> DIVP.
154 * struct tegra_clk_pll_freq_table - PLL frequecy table
157 * @output_rate: output rate from PLL for the input rate
175 * struct pdiv_map - map post divider to hw value
178 * @hw_val: value to be written to the PLL hw
186 * struct div_nmp - offset and width of m,n and p fields
215 * struct tegra_clk_pll_params - PLL parameters
223 * @base_reg: PLL base reg offset
224 * @misc_reg: PLL misc reg offset
225 * @lock_reg: PLL lock reg offset
226 * @lock_mask: Bitmask for PLL lock status
227 * @lock_enable_bit_idx: Bit index to enable PLL lock
228 * @iddq_reg: PLL IDDQ register offset
229 * @iddq_bit_idx: Bit index to enable PLL IDDQ
243 * @flags: PLL flags
246 * @lock_delay: Delay in us if PLL lock is not used
248 * @defaults_set: Boolean signaling all reg defaults for PLL set.
251 * @freq_table: array of frequencies supported by PLL
252 * @fixed_rate: PLL rate if it is fixed
253 * @mdiv_default: Default value for fixed mdiv for this PLL
256 * PLL's based on fractional divider value.
261 * @set_defaults: Callback which will try to initialize PLL
263 * tried during PLL registration, but if the PLL
265 * time the rate is changed while the PLL is
268 * dynamic ramp function for a given PLL.
270 * PLL's rate.
272 * PLL's rate.
275 * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for
276 * PLL locking. If not set it will use lock_delay value to wait.
277 * TEGRA_PLL_HAS_CPCON - This flag indicates that CPCON value needs
278 * to be programmed to change output frequency of the PLL.
279 * TEGRA_PLL_SET_LFCON - This flag indicates that LFCON value needs
280 * to be programmed to change output frequency of the PLL.
281 * TEGRA_PLL_SET_DCCON - This flag indicates that DCCON value needs
282 * to be programmed to change output frequency of the PLL.
283 * TEGRA_PLLU - PLLU has inverted post divider. This flags indicated
285 * TEGRA_PLLM - PLLM has additional override settings in PMC. This
287 * TEGRA_PLL_FIXED - We are not supposed to change output frequency
289 * TEGRA_PLLE_CONFIGURE - Configure PLLE when enabling.
290 * TEGRA_PLL_LOCK_MISC - Lock bit is in the misc register instead of the
292 * TEGRA_PLL_BYPASS - PLL has bypass bit
293 * TEGRA_PLL_HAS_LOCK_ENABLE - PLL has bit to enable lock monitoring
294 * TEGRA_MDIV_NEW - Switch to new method for calculating fixed mdiv
296 * TEGRA_PLLMB - PLLMB has should be treated similar to PLLM. This
298 * TEGRA_PLL_VCO_OUT - Used to indicate that the PLL has a VCO output
346 void (*set_defaults)(struct tegra_clk_pll *pll);
347 int (*dyn_ramp)(struct tegra_clk_pll *pll,
369 * struct tegra_clk_pll - Tegra PLL clock
371 * @hw: handle between common and hardware-specifix interfaces
375 * @params: PLL parameters
388 * struct tegra_audio_clk_info - Tegra Audio Clk Information
390 * @name: name for the audio pll
391 * @pll_params: pll_params for audio pll
392 * @clk_id: clk_ids for the audio pll
393 * @parent: name of the parent of the audio pll
497 * struct tegra_clk_pll_out - PLL divider down clock
499 * @hw: handle between common and hardware-specific interfaces
500 * @reg: register containing the PLL divider
501 * @enb_bit_idx: bit to enable/disable PLL divider
502 * @rst_bit_idx: bit to reset PLL divider
504 * @flags: hardware-specific flags
524 * struct tegra_clk_periph_regs - Registers controlling peripheral clock
543 * struct tegra_clk_periph_gate - peripheral gate clock
546 * @hw: handle between common and hardware-specific interfaces
549 * @flags: hardware-specific flags
554 * TEGRA_PERIPH_NO_RESET - This flag indicates that reset is not allowed
556 * TEGRA_PERIPH_ON_APB - If peripheral is in the APB bus then read the
559 * TEGRA_PERIPH_WAR_1005168 - Apply workaround for Tegra114 MSENC bug
605 * struct clk-periph - peripheral clock
608 * @hw: handle between common and hardware-specific interfaces
635 struct tegra_clk_periph *periph, void __iomem *clk_base,
639 struct tegra_clk_periph *periph, void __iomem *clk_base,
678 struct tegra_clk_periph periph; member
695 .periph = TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, \
711 _mux_shift, BIT(_mux_width) - 1, _mux_flags, \
720 * struct clk_super_mux - super clock
722 * @hw: handle between common and hardware-specific interfaces
725 * @flags: hardware-specific flags
726 * @div2_index: bit controlling divide-by-2
731 * TEGRA_DIVIDER_2 - LP cluster has additional divider. This flag indicates
733 * TEGRA210_CPU_CLK - This flag is used to identify CPU cluster for gen5
736 * TEGRA20_SUPER_CLK - Tegra20 doesn't have a dedicated divider for Super
737 * clocks, it only has a clock-skipper.
774 * struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC
776 * @hw: handle between common and hardware-specific interfaces
778 * @flags: hardware-specific flags
799 * struct clk_init_table - clock initialization table
813 * struct clk_duplicate - duplicate clocks
906 int tegra_pll_wait_for_lock(struct tegra_clk_pll *pll);
908 int tegra_pll_p_div_to_hw(struct tegra_clk_pll *pll, u8 p_div);