Lines Matching full:clk_m
593 { .con_id = "clk_m", .dt_id = TEGRA30_CLK_CLK_M },
878 static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
881 static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
885 static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
973 "clk_m" };
974 static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" };
976 "clk_m" };
980 "pll_d2_out0", "clk_m" };
983 static const char *pwm_parents[] = { "pll_p", "pll_c", "clk_32k", "clk_m" };
1013 clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0, in tegra30_periph_clk_init()
1018 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72, in tegra30_periph_clk_init()
1123 /* switch coresite to clk_m, save off original source */ in tegra30_cpu_clock_suspend()