Lines Matching +full:- +full:12000000
1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
18 #include <dt-bindings/clock/tegra30-car.h>
21 #include "clk-id.h"
187 { 12000000, 1040000000, 520, 6, 1, 8 },
192 { 12000000, 832000000, 416, 6, 1, 8 },
197 { 12000000, 624000000, 624, 12, 1, 8 },
202 { 12000000, 600000000, 600, 12, 1, 8 },
207 { 12000000, 520000000, 520, 12, 1, 8 },
212 { 12000000, 416000000, 416, 12, 1, 8 },
221 { 12000000, 666000000, 666, 12, 1, 8 },
226 { 12000000, 600000000, 600, 12, 1, 8 },
235 { 12000000, 216000000, 432, 12, 2, 8 },
254 { 12000000, 216000000, 216, 12, 1, 4 },
259 { 12000000, 594000000, 594, 12, 1, 8 },
264 { 12000000, 1000000000, 1000, 12, 1, 12 },
278 { 12000000, 480000000, 960, 12, 2, 12 },
288 { 12000000, 1700000000, 850, 6, 1, 8 },
294 { 12000000, 1600000000, 800, 6, 1, 8 },
300 { 12000000, 1500000000, 750, 6, 1, 8 },
306 { 12000000, 1400000000, 700, 6, 1, 8 },
312 { 12000000, 1300000000, 975, 9, 1, 8 },
318 { 12000000, 1200000000, 1000, 10, 1, 8 },
324 { 12000000, 1100000000, 825, 9, 1, 8 },
330 { 12000000, 1000000000, 1000, 12, 1, 8 },
346 { 12000000, 100000000, 150, 1, 18, 11 },
509 .input_min = 12000000,
511 .cf_min = 12000000,
512 .cf_max = 12000000,
532 [ 8] = 12000000,
595 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_VCP },
596 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_BSEA },
597 { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA30_CLK_BSEV },
601 { .con_id = "pcie", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIE },
602 { .con_id = "afi", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_AFI },
604 { .con_id = "fuse_burn", .dev_id = "fuse-tegra", .dt_id = TEGRA30_CLK_FUSE_BURN },
605 { .con_id = "apbif", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_APBIF },
606 { .con_id = "hda2hdmi", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2HDMI },
607 { .dev_id = "tegra-apbdma", .dt_id = TEGRA30_CLK_APBDMA },
608 { .dev_id = "rtc-tegra", .dt_id = TEGRA30_CLK_RTC },
610 { .dev_id = "tegra-kbc", .dt_id = TEGRA30_CLK_KBC },
611 { .dev_id = "fsl-tegra-udc", .dt_id = TEGRA30_CLK_USBD },
612 { .dev_id = "tegra-ehci.1", .dt_id = TEGRA30_CLK_USB2 },
613 { .dev_id = "tegra-ehci.2", .dt_id = TEGRA30_CLK_USB2 },
614 { .dev_id = "kfuse-tegra", .dt_id = TEGRA30_CLK_KFUSE },
617 { .dev_id = "tegra30-i2s.0", .dt_id = TEGRA30_CLK_I2S0 },
618 { .dev_id = "tegra30-i2s.1", .dt_id = TEGRA30_CLK_I2S1 },
619 { .dev_id = "tegra30-i2s.2", .dt_id = TEGRA30_CLK_I2S2 },
620 { .dev_id = "tegra30-i2s.3", .dt_id = TEGRA30_CLK_I2S3 },
621 { .dev_id = "tegra30-i2s.4", .dt_id = TEGRA30_CLK_I2S4 },
622 { .con_id = "spdif_out", .dev_id = "tegra30-spdif", .dt_id = TEGRA30_CLK_SPDIF_OUT },
623 { .con_id = "spdif_in", .dev_id = "tegra30-spdif", .dt_id = TEGRA30_CLK_SPDIF_IN },
624 { .con_id = "d_audio", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_D_AUDIO },
625 { .dev_id = "tegra30-dam.0", .dt_id = TEGRA30_CLK_DAM0 },
626 { .dev_id = "tegra30-dam.1", .dt_id = TEGRA30_CLK_DAM1 },
627 { .dev_id = "tegra30-dam.2", .dt_id = TEGRA30_CLK_DAM2 },
628 { .con_id = "hda", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA },
629 { .con_id = "hda2codec_2x", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2CODEC_2X },
645 { .dev_id = "tegra-tsensor", .dt_id = TEGRA30_CLK_TSENSOR },
657 { .dev_id = "tegra-nor", .dt_id = TEGRA30_CLK_NOR },
658 { .dev_id = "sdhci-tegra.0", .dt_id = TEGRA30_CLK_SDMMC1 },
659 { .dev_id = "sdhci-tegra.1", .dt_id = TEGRA30_CLK_SDMMC2 },
660 { .dev_id = "sdhci-tegra.2", .dt_id = TEGRA30_CLK_SDMMC3 },
661 { .dev_id = "sdhci-tegra.3", .dt_id = TEGRA30_CLK_SDMMC4 },
667 { .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA30_CLK_I2C1 },
668 { .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA30_CLK_I2C2 },
669 { .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA30_CLK_I2C3 },
670 { .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA30_CLK_I2C4 },
671 { .con_id = "div-clk", .dev_id = "tegra-i2c.4", .dt_id = TEGRA30_CLK_I2C5 },
1043 clks[data->clk_id] = clk; in tegra30_periph_clk_init()
1048 clk = tegra_clk_register_periph_nodiv(data->name, in tegra30_periph_clk_init()
1049 data->p.parent_names, in tegra30_periph_clk_init()
1050 data->num_parents, &data->periph, in tegra30_periph_clk_init()
1051 clk_base, data->offset); in tegra30_periph_clk_init()
1052 clks[data->clk_id] = clk; in tegra30_periph_clk_init()
1250 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "utmip-pad", NULL),
1251 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "tegra-ehci.0", NULL),
1252 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "tegra-otg", NULL),
1253 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEV, "tegra-avp", "bsev"),
1255 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VDE, "tegra-aes", "vde"),
1256 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEA, "tegra-aes", "bsea"),
1266 { .compatible = "nvidia,tegra30-pmc" },
1286 if (clkspec->args[0] != TEGRA30_CLK_RTC && in tegra30_clk_src_onecell_get()
1287 clkspec->args[0] != TEGRA30_CLK_TWD && in tegra30_clk_src_onecell_get()
1288 clkspec->args[0] != TEGRA30_CLK_TIMER && in tegra30_clk_src_onecell_get()
1290 return ERR_PTR(-EPROBE_DEFER); in tegra30_clk_src_onecell_get()
1298 if (clkspec->args[0] == TEGRA30_CLK_EMC) { in tegra30_clk_src_onecell_get()
1300 return ERR_PTR(-EPROBE_DEFER); in tegra30_clk_src_onecell_get()
1353 CLK_OF_DECLARE_DRIVER(tegra30, "nvidia,tegra30-car", tegra30_clock_init);
1399 { .compatible = "nvidia,tegra30-car" },
1405 .name = "tegra30-car",
1415 * from arch init-level.