Lines Matching refs:readl_relaxed
504 value = readl_relaxed(clk_base + PLLE_AUX);
520 value = readl_relaxed(clk_base + PLLE_MISC0);
527 value = readl_relaxed(clk_base + PLLE_AUX);
547 val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0);
560 val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0);
570 val = readl_relaxed(clk_base + SATA_PLL_CFG0);
582 val = readl_relaxed(clk_base + SATA_PLL_CFG0);
592 val = readl_relaxed(clk_base + SATA_PLL_CFG0);
633 val = readl_relaxed(clk_base + mbist->lvl2_offset);
647 csi_src = readl_relaxed(clk_base + PLLD_BASE);
651 ovra = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRA);
653 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE);
669 ovra = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRA);
673 dsc_top_ctrl = readl_relaxed(dispa_base + DC_COM_DSC_TOP_CTL);
675 readl_relaxed(dispa_base + DC_CMD_DISPLAY_COMMAND);
677 readl_relaxed(dispa_base + DC_CMD_DISPLAY_COMMAND);
687 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE);
691 val = readl_relaxed(vic_base + NV_PVIC_THI_SLCG_OVERRIDE_LOW);
709 ovrc = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRC);
710 ovre = readl_relaxed(clk_base + LVL2_CLK_GATE_OVRE);
721 i2s_ctrl = readl_relaxed(i2s_base + TEGRA210_I2S_CTRL);
742 u32 boot_val = readl_relaxed(base + params->ext_misc_reg[misc_num]);
785 if (readl_relaxed(clk_base + pllcx->params->base_reg) & PLL_ENABLE) {
834 u32 val = readl_relaxed(clk_base + plla->params->base_reg);
860 val = readl_relaxed(clk_base + plla->params->ext_misc_reg[0]);
890 if (readl_relaxed(clk_base + plld->params->base_reg) &
913 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]);
922 val = readl_relaxed(clk_base + plld->params->ext_misc_reg[0]);
940 u32 val = readl_relaxed(clk_base + plldss->params->base_reg);
994 val = readl_relaxed(clk_base + plldss->params->ext_misc_reg[0]);
1059 u32 val = readl_relaxed(clk_base + pllre->params->base_reg);
1084 val = readl_relaxed(clk_base + pllre->params->ext_misc_reg[0]);
1188 if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) {
1202 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[0]);
1237 u32 mask, val = readl_relaxed(clk_base + pllmb->params->base_reg);
1255 val = readl_relaxed(clk_base + pllmb->params->ext_misc_reg[0]);
1298 u32 val = readl_relaxed(clk_base + pllp->params->base_reg);
1313 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[0]);
1328 val = readl_relaxed(clk_base + pllp->params->ext_misc_reg[1]);
1361 u32 val = readl_relaxed(clk_base + pllu->base_reg);
1376 val = readl_relaxed(clk_base + pllu->ext_misc_reg[0]);
1381 val = readl_relaxed(clk_base + pllu->ext_misc_reg[1]);
1421 val = readl_relaxed(clk_base + reg);
1438 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]);
1444 val = readl_relaxed(clk_base + pllx->params->ext_misc_reg[2]);
1452 base = readl_relaxed(clk_base + pllx->params->base_reg) &
2779 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2795 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2817 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2823 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
2836 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
2850 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
2858 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
2868 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
2873 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2880 reg = readl_relaxed(clk_base + XUSB_PLL_CFG0);
2887 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
2911 reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]);
2916 reg = readl_relaxed(clk_base + PLLU_BASE);
2948 reg = readl_relaxed(clk_base + PLLU_BASE);
2958 reg = readl_relaxed(clk_base + PLLU_BASE);
2962 reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0);
2970 reg = readl_relaxed(clk_base + XUSB_PLL_CFG0);
2975 reg = readl_relaxed(clk_base + PLLU_HW_PWRDN_CFG0);
2980 reg = readl_relaxed(clk_base + PLLU_BASE);
2986 reg = readl_relaxed(clk_base + UTMIPLL_HW_PWRDN_CFG0);
3440 #define car_readl(_base, _off) readl_relaxed(clk_base + (_base) + ((_off) * 4))
3457 spare_reg_ctx = readl_relaxed(clk_base + SPARE_REG0);
3458 misc_clk_enb_ctx = readl_relaxed(clk_base + MISC_CLK_ENB);
3459 clk_msk_arm_ctx = readl_relaxed(clk_base + CLK_MASK_ARM);
3626 readl_relaxed(clk_base + RST_DFLL_DVCO);
3638 v = readl_relaxed(clk_base + RST_DFLL_DVCO);
3654 v = readl_relaxed(clk_base + RST_DFLL_DVCO);