Lines Matching refs:pllu
1359 static void tegra210_pllu_set_defaults(struct tegra_clk_pll_params *pllu) in tegra210_pllu_set_defaults() argument
1361 u32 val = readl_relaxed(clk_base + pllu->base_reg); in tegra210_pllu_set_defaults()
1363 pllu->defaults_set = true; in tegra210_pllu_set_defaults()
1371 pllu_check_defaults(pllu, false); in tegra210_pllu_set_defaults()
1372 if (!pllu->defaults_set) in tegra210_pllu_set_defaults()
1376 val = readl_relaxed(clk_base + pllu->ext_misc_reg[0]); in tegra210_pllu_set_defaults()
1379 writel_relaxed(val, clk_base + pllu->ext_misc_reg[0]); in tegra210_pllu_set_defaults()
1381 val = readl_relaxed(clk_base + pllu->ext_misc_reg[1]); in tegra210_pllu_set_defaults()
1384 writel_relaxed(val, clk_base + pllu->ext_misc_reg[1]); in tegra210_pllu_set_defaults()
1392 clk_base + pllu->ext_misc_reg[0]); in tegra210_pllu_set_defaults()
1394 clk_base + pllu->ext_misc_reg[1]); in tegra210_pllu_set_defaults()
2895 struct tegra_clk_pll pllu; in tegra210_enable_pllu() local
2910 pllu.params = &pll_u_vco_params; in tegra210_enable_pllu()
2911 reg = readl_relaxed(clk_base + pllu.params->ext_misc_reg[0]); in tegra210_enable_pllu()
2912 reg &= ~BIT(pllu.params->iddq_bit_idx); in tegra210_enable_pllu()
2913 writel_relaxed(reg, clk_base + pllu.params->ext_misc_reg[0]); in tegra210_enable_pllu()
2932 ret = tegra210_wait_for_mask(&pllu, PLLU_BASE, PLL_BASE_LOCK); in tegra210_enable_pllu()