Lines Matching +full:tegra124 +full:- +full:mc

1 // SPDX-License-Identifier: GPL-2.0-only
3  * Copyright (c) 2012-2014 NVIDIA CORPORATION.  All rights reserved.
7 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/tegra124-car.h>
15 #include <dt-bindings/reset/tegra124-car.h>
18 #include "clk-id.h"
22  * banks present in the Tegra124/132 CAR IP block.  The banks are
95 #define MASK(x) (BIT(x) - 1)
995 	{ .dev_id = "rtc-tegra", .dt_id = TEGRA124_CLK_RTC },
1053 	clk = tegra_clk_register_mc("mc", "emc", clk_base + CLK_SOURCE_EMC,  in tegra124_periph_clk_init()
1073 		clkp = tegra_lookup_dt_id(init->clk_id, tegra124_clks);  in tegra124_periph_clk_init()
1075 			pr_warn("clock %u not found\n", init->clk_id);  in tegra124_periph_clk_init()
1234 /* Tegra124 CPU clock and reset control functions */
1286 	{ .compatible = "nvidia,tegra124-pmc" },
1359  * tegra124_clock_apply_init_table - initialize clocks on Tegra124 SoCs
1362  * by the rest of the kernel, for Tegra124 SoCs.  It is intended to be
1363  * called by assigning a pointer to it to tegra_clk_apply_init_table -
1373  * tegra124_car_barrier - wait for pending writes to the CAR to complete
1384  * tegra124_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset
1399  * tegra124_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset
1419 		return -EINVAL;  in tegra124_reset_assert()
1429 		return -EINVAL;  in tegra124_reset_deassert()
1435  * tegra132_clock_apply_init_table - initialize clocks on Tegra132 SoCs
1439  * called by assigning a pointer to it to tegra_clk_apply_init_table -
1449  * tegra124_132_clock_init_pre - clock initialization preamble for T124/T132
1453  * Everything in this function should be common to Tegra124 and Tegra132.
1463 		pr_err("ioremap tegra124/tegra132 CAR failed\n");  in tegra124_132_clock_init_pre()
1499 	/* For Tegra124 & Tegra132, PLLD is the only source for DSIA & DSIB */  in tegra124_132_clock_init_pre()
1517 	if (clkspec->args[0] == TEGRA124_CLK_EMC) {  in tegra124_clk_src_onecell_get()
1519 			return ERR_PTR(-EPROBE_DEFER);  in tegra124_clk_src_onecell_get()
1526  * tegra124_132_clock_init_post - clock initialization postamble for T124/T132
1530  * Everything in this function should be common to Tegra124
1552  * tegra124_clock_init - Tegra124-specific clock initialization
1555  * Register most SoC clocks for the Tegra124 system-on-chip.  Most of
1556  * this code is shared between the Tegra124 and Tegra132 SoCs,
1559  * "nvidia,tegra124-car" string is encountered, and declared with
1570  * tegra132_clock_init - Tegra132-specific clock initialization
1573  * Register most SoC clocks for the Tegra132 system-on-chip.  Most of
1574  * this code is shared between the Tegra124 and Tegra132 SoCs,
1577  * "nvidia,tegra132-car" string is encountered, and declared with
1596 CLK_OF_DECLARE(tegra124, "nvidia,tegra124-car", tegra124_clock_init);
1597 CLK_OF_DECLARE(tegra132, "nvidia,tegra132-car", tegra132_clock_init);