Lines Matching +full:tegra210 +full:- +full:adx

1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
16 #include "clk-id.h"
130 #define MASK(x) (BIT(x) - 1)
648 MUX("adx", mux_plla_pllc_pllp_clkm, CLK_SOURCE_ADX, 154, TEGRA_PERIPH_ON_APB, tegra_clk_adx),
787 GATE("mipi-cal", "clk72mhz", 56, 0, tegra_clk_mipi_cal, 0),
873 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); in periph_clk_init()
877 bank = get_reg_bank(data->periph.gate.clk_num); in periph_clk_init()
881 data->periph.gate.regs = bank; in periph_clk_init()
899 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); in gate_clk_init()
903 clk = tegra_clk_register_periph_gate(data->name, in gate_clk_init()
904 data->p.parent_name, data->periph.gate.flags, in gate_clk_init()
905 clk_base, data->flags, in gate_clk_init()
906 data->periph.gate.clk_num, in gate_clk_init()
924 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); in div_clk_init()
928 clk = tegra_clk_register_divider(data->name, in div_clk_init()
929 data->p.parent_name, clk_base + data->offset, in div_clk_init()
930 data->flags, data->periph.divider.flags, in div_clk_init()
931 data->periph.divider.shift, in div_clk_init()
932 data->periph.divider.width, in div_clk_init()
933 data->periph.divider.frac_width, in div_clk_init()
934 data->periph.divider.lock); in div_clk_init()
961 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); in init_pllp()
965 clk = tegra_clk_register_divider(data->div_name, "pll_p", in init_pllp()
966 clk_base + data->offset, 0, data->div_flags, in init_pllp()
967 data->div_shift, 8, 1, data->lock); in init_pllp()
968 clk = tegra_clk_register_pll_out(data->pll_out_name, in init_pllp()
969 data->div_name, clk_base + data->offset, in init_pllp()
970 data->rst_shift + 1, data->rst_shift, in init_pllp()
972 data->lock); in init_pllp()
980 * Tegra210 has control on enabling/disabling PLLP branches to in init_pllp()
983 * re-parenting CPU off from "pll_p_out4" the PLLP branching to in init_pllp()