1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
15 #include "clk-id.h"
38 #define SYNC(_name) \  macro
95 	SYNC(spdif_in_sync),
96 	SYNC(i2s0_sync),
97 	SYNC(i2s1_sync),
98 	SYNC(i2s2_sync),
99 	SYNC(i2s3_sync),
100 	SYNC(i2s4_sync),
101 	SYNC(vimclk_sync),
130 				      struct tegra_audio_clk_initdata *sync,  in tegra_audio_sync_clk_init()  argument
140 	for (i = 0, data = sync; i < num_sync_clks; i++, data++) {  in tegra_audio_sync_clk_init()
141 		dt_clk = tegra_lookup_dt_id(data->mux_clk_id, tegra_clks);  in tegra_audio_sync_clk_init()
145 		clk = clk_register_mux(NULL, data->mux_name, mux_names,  in tegra_audio_sync_clk_init()
148 					clk_base + data->offset, 0, 3, 0,  in tegra_audio_sync_clk_init()
152 		dt_clk = tegra_lookup_dt_id(data->gate_clk_id, tegra_clks);  in tegra_audio_sync_clk_init()
156 		clk = clk_register_gate(NULL, data->gate_name, data->mux_name,  in tegra_audio_sync_clk_init()
157 					0, clk_base + data->offset, 4,  in tegra_audio_sync_clk_init()
172 	if (!audio_info || num_plls < 1) {  in tegra_audio_clk_init()
174 		WARN_ON(1);  in tegra_audio_clk_init()
181 		dt_clk = tegra_lookup_dt_id(info->clk_id, tegra_clks);  in tegra_audio_clk_init()
183 			clk = tegra_clk_register_pll(info->name, info->parent,  in tegra_audio_clk_init()
184 					clk_base, pmc_base, 0, info->pll_params,  in tegra_audio_clk_init()
195 				8, 8, 1, NULL);  in tegra_audio_clk_init()
197 				clk_base + PLLA_OUT, 1, 0, CLK_IGNORE_UNUSED |  in tegra_audio_clk_init()
207 		dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);  in tegra_audio_clk_init()
211 		clk = tegra_clk_register_sync_source(data->name, sync_max_rate);  in tegra_audio_clk_init()
219 	/* make sure the DMIC sync clocks have a valid parent */  in tegra_audio_clk_init()
221 		writel_relaxed(1, clk_base + dmic_clks[i].offset);  in tegra_audio_clk_init()
231 		dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks);  in tegra_audio_clk_init()
235 		clk = clk_register_fixed_factor(NULL, data->name_2x,  in tegra_audio_clk_init()
236 				data->parent, CLK_SET_RATE_PARENT, 2, 1);  in tegra_audio_clk_init()
237 		clk = tegra_clk_register_divider(data->div_name,  in tegra_audio_clk_init()
238 				data->name_2x, clk_base + AUDIO_SYNC_DOUBLER,  in tegra_audio_clk_init()
239 				0, 0, data->div_offset, 1, 0,  in tegra_audio_clk_init()
241 		clk = tegra_clk_register_periph_gate(data->gate_name,  in tegra_audio_clk_init()
242 				data->div_name, TEGRA_PERIPH_NO_RESET,  in tegra_audio_clk_init()
243 				clk_base, CLK_SET_RATE_PARENT, data->clk_num,  in tegra_audio_clk_init()