Lines Matching full:periph

16 	struct tegra_clk_periph *periph = to_clk_periph(hw);
17 	const struct clk_ops *mux_ops = periph->mux_ops;
18 	struct clk_hw *mux_hw = &periph->mux.hw;
27 	struct tegra_clk_periph *periph = to_clk_periph(hw);
28 	const struct clk_ops *mux_ops = periph->mux_ops;
29 	struct clk_hw *mux_hw = &periph->mux.hw;
39 	struct tegra_clk_periph *periph = to_clk_periph(hw);
40 	const struct clk_ops *div_ops = periph->div_ops;
41 	struct clk_hw *div_hw = &periph->divider.hw;
51 	struct tegra_clk_periph *periph = to_clk_periph(hw);
52 	const struct clk_ops *div_ops = periph->div_ops;
53 	struct clk_hw *div_hw = &periph->divider.hw;
69 	struct tegra_clk_periph *periph = to_clk_periph(hw);
70 	const struct clk_ops *div_ops = periph->div_ops;
71 	struct clk_hw *div_hw = &periph->divider.hw;
80 	struct tegra_clk_periph *periph = to_clk_periph(hw);
81 	const struct clk_ops *gate_ops = periph->gate_ops;
82 	struct clk_hw *gate_hw = &periph->gate.hw;
91 	struct tegra_clk_periph *periph = to_clk_periph(hw);
92 	const struct clk_ops *gate_ops = periph->gate_ops;
93 	struct clk_hw *gate_hw = &periph->gate.hw;
102 	struct tegra_clk_periph *periph = to_clk_periph(hw);
103 	const struct clk_ops *gate_ops = periph->gate_ops;
104 	struct clk_hw *gate_hw = &periph->gate.hw;
111 	struct tegra_clk_periph *periph = to_clk_periph(hw);
112 	const struct clk_ops *gate_ops = periph->gate_ops;
113 	struct clk_hw *gate_hw = &periph->gate.hw;
120 	struct tegra_clk_periph *periph = to_clk_periph(hw);
121 	const struct clk_ops *div_ops = periph->div_ops;
122 	struct clk_hw *div_hw = &periph->divider.hw;
129 	if (!(periph->gate.flags & TEGRA_PERIPH_NO_DIV))
170 			struct tegra_clk_periph *periph,
177 	bool div = !(periph->gate.flags & TEGRA_PERIPH_NO_DIV);
179 	if (periph->gate.flags & TEGRA_PERIPH_NO_DIV) {
182 	} else if (periph->gate.flags & TEGRA_PERIPH_NO_GATE)
192 	bank = get_reg_bank(periph->gate.clk_num);
197 	periph->hw.init = &init;
198 	periph->magic = TEGRA_CLK_PERIPH_MAGIC;
199 	periph->mux.reg = clk_base + offset;
200 	periph->divider.reg = div ? (clk_base + offset) : NULL;
201 	periph->gate.clk_base = clk_base;
202 	periph->gate.regs = bank;
203 	periph->gate.enable_refcnt = periph_clk_enb_refcnt;
205 	clk = clk_register(NULL, &periph->hw);
209 	periph->mux.hw.clk = clk;
210 	periph->divider.hw.clk = div ? clk : NULL;
211 	periph->gate.hw.clk = clk;
218 		struct tegra_clk_periph *periph, void __iomem *clk_base,
222 			periph, clk_base, offset, flags);
227 		struct tegra_clk_periph *periph, void __iomem *clk_base,
230 	periph->gate.flags |= TEGRA_PERIPH_NO_DIV;
232 			periph, clk_base, offset, CLK_SET_RATE_PARENT);
239 					  init->num_parents, &init->periph,