1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
14 #define pll_out_override(p) (BIT((p->shift - 6)))
15 #define div_mask(d) ((1 << (d->width)) - 1)
16 #define get_mul(d) (1 << d->frac_width)
24 	int div;  in get_div()  local
26 	div = div_frac_get(rate, parent_rate, divider->width,  in get_div()
27 			   divider->frac_width, divider->flags);  in get_div()
29 	if (div < 0)  in get_div()
32 	return div;  in get_div()
39 	u32 reg;  in clk_frac_div_recalc_rate()  local
40 	int div, mul;  in clk_frac_div_recalc_rate()  local
43 	reg = readl_relaxed(divider->reg);  in clk_frac_div_recalc_rate()
45 	if ((divider->flags & TEGRA_DIVIDER_UART) &&  in clk_frac_div_recalc_rate()
46 	    !(reg & PERIPH_CLK_UART_DIV_ENB))  in clk_frac_div_recalc_rate()
49 	div = (reg >> divider->shift) & div_mask(divider);  in clk_frac_div_recalc_rate()
52 	div += mul;  in clk_frac_div_recalc_rate()
55 	rate += div - 1;  in clk_frac_div_recalc_rate()
56 	do_div(rate, div);  in clk_frac_div_recalc_rate()
65 	int div, mul;  in clk_frac_div_determine_rate()  local
66 	unsigned long output_rate = req->best_parent_rate;  in clk_frac_div_determine_rate()
68 	if (!req->rate) {  in clk_frac_div_determine_rate()
69 		req->rate = output_rate;  in clk_frac_div_determine_rate()
74 	div = get_div(divider, req->rate, output_rate);  in clk_frac_div_determine_rate()
75 	if (div < 0) {  in clk_frac_div_determine_rate()
76 		req->rate = req->best_parent_rate;  in clk_frac_div_determine_rate()
83 	req->rate = DIV_ROUND_UP(output_rate * mul, div + mul);  in clk_frac_div_determine_rate()
92 	int div;  in clk_frac_div_set_rate()  local
96 	div = get_div(divider, rate, parent_rate);  in clk_frac_div_set_rate()
97 	if (div < 0)  in clk_frac_div_set_rate()
98 		return div;  in clk_frac_div_set_rate()
100 	if (divider->lock)  in clk_frac_div_set_rate()
101 		spin_lock_irqsave(divider->lock, flags);  in clk_frac_div_set_rate()
103 	val = readl_relaxed(divider->reg);  in clk_frac_div_set_rate()
104 	val &= ~(div_mask(divider) << divider->shift);  in clk_frac_div_set_rate()
105 	val |= div << divider->shift;  in clk_frac_div_set_rate()
107 	if (divider->flags & TEGRA_DIVIDER_UART) {  in clk_frac_div_set_rate()
108 		if (div)  in clk_frac_div_set_rate()
114 	if (divider->flags & TEGRA_DIVIDER_FIXED)  in clk_frac_div_set_rate()
117 	writel_relaxed(val, divider->reg);  in clk_frac_div_set_rate()
119 	if (divider->lock)  in clk_frac_div_set_rate()
120 		spin_unlock_irqrestore(divider->lock, flags);  in clk_frac_div_set_rate()
143 		const char *parent_name, void __iomem *reg,  in tegra_clk_register_divider()  argument
155 		return ERR_PTR(-ENOMEM);  in tegra_clk_register_divider()
164 	divider->reg = reg;  in tegra_clk_register_divider()
165 	divider->shift = shift;  in tegra_clk_register_divider()
166 	divider->width = width;  in tegra_clk_register_divider()
167 	divider->frac_width = frac_width;  in tegra_clk_register_divider()
168 	divider->lock = lock;  in tegra_clk_register_divider()
169 	divider->flags = clk_divider_flags;  in tegra_clk_register_divider()
172 	divider->hw.init = &init;  in tegra_clk_register_divider()
174 	clk = clk_register(NULL, &divider->hw);  in tegra_clk_register_divider()
182 	{ .val = 0, .div = 2 },
183 	{ .val = 1, .div = 1 },
184 	{ .val = 0, .div = 0 },
188 				  void __iomem *reg, spinlock_t *lock)  in tegra_clk_register_mc()  argument
192 					  reg, 16, 1, CLK_DIVIDER_READ_ONLY,  in tegra_clk_register_mc()