Lines Matching full:lut
186 /* MAX_DFLL_VOLTAGES: number of LUT entries in the DFLL IP block */
248 * @lut_index: LUT index at which voltage the dvco_target_rate will be reached
302 /* lut array entries are regulator framework selectors or PWM values*/
303 unsigned lut[MAX_DFLL_VOLTAGES]; member
690 td->lut[lut_index]); in dfll_load_i2c_lut()
787 * find_lut_index_for_rate - determine I2C LUT index for given DFLL rate
791 * Determines the index of a I2C LUT entry for a voltage that approximately
794 * LUT index is not found.
1660 td->lut[i] = i; in dfll_build_pwm_lut()
1698 * On success, fills in td->lut and returns 0, or -err on failure.
1704 int j, selector, lut; in dfll_build_i2c_lut() local
1707 lut = find_vdd_map_entry_exact(td, v); in dfll_build_i2c_lut()
1708 if (lut < 0) in dfll_build_i2c_lut()
1710 td->lut[0] = lut; in dfll_build_i2c_lut()
1734 if (selector != td->lut[j - 1]) in dfll_build_i2c_lut()
1735 td->lut[j++] = selector; in dfll_build_i2c_lut()
1742 if (selector != td->lut[j - 1]) in dfll_build_i2c_lut()
1743 td->lut[j++] = selector; in dfll_build_i2c_lut()
1758 td->lut[j]); in dfll_build_i2c_lut()
1994 dev_err(td->dev, "couldn't build LUT\n"); in tegra_dfll_register()