Lines Matching +full:closed +full:- +full:loop
1 // SPDX-License-Identifier: GPL-2.0-only
3 * clk-dfll.c - Tegra DFLL clock source common code
5 * Copyright (C) 2012-2019 NVIDIA Corporation. All rights reserved.
12 * "CL-DVFS". To try to avoid confusion, this code refers to them
18 * DFLL can be operated in either open-loop mode or closed-loop mode.
19 * In open-loop mode, the DFLL generates an output clock appropriate
20 * to the supply voltage. In closed-loop mode, when configured with a
27 * performance-measurement code and any code that relies on the CPU
32 #include <linux/clk-provider.h>
49 #include "clk-dfll.h"
53 * DFLL control registers - access via dfll_{readl,writel}
65 /* DFLL_PARAMS: tuning coefficients for closed loop integrator */
89 #define FORCE_MIN -2048
101 /* DFLL_OUTPUT_CFG: closed loop mode control registers */
121 /* DFLL_OUTPUT_FORCE: closed loop mode voltage forcing control */
139 * I2C output control registers - access via dfll_i2c_{readl,writel}
154 /* DFLL_I2C_VDD_REG_ADDR: PMIC I2C address for closed loop mode */
171 * Integrated I2C controller registers - relative to td->i2c_controller_base
191 * integrates the DVCO counter over - used for debug rate monitoring and
206 * enum dfll_ctrl_mode - DFLL hardware operating mode
207 * @DFLL_UNINITIALIZED: (uninitialized state - not in hardware bitfield)
224 * enum dfll_tune_range - voltage range that the driver believes it's in
226 * @DFLL_TUNE_LOW: DFLL in the low-voltage range (or open-loop mode)
245 * struct dfll_rate_req - target DFLL rate request data
333 return __raw_readl(td->base + offs); in dfll_readl()
339 __raw_writel(val, td->base + offs); in dfll_writel()
347 /* I2C output control registers - for addresses above DFLL_I2C_CFG */
351 return __raw_readl(td->i2c_base + offs); in dfll_i2c_readl()
356 __raw_writel(val, td->i2c_base + offs); in dfll_i2c_writel()
365 * dfll_is_running - is the DFLL currently generating a clock?
373 return td->mode >= DFLL_OPEN_LOOP; in dfll_is_running()
381 * tegra_dfll_runtime_resume - enable all clocks needed by the DFLL
394 ret = clk_enable(td->ref_clk); in tegra_dfll_runtime_resume()
400 ret = clk_enable(td->soc_clk); in tegra_dfll_runtime_resume()
403 clk_disable(td->ref_clk); in tegra_dfll_runtime_resume()
407 ret = clk_enable(td->i2c_clk); in tegra_dfll_runtime_resume()
410 clk_disable(td->soc_clk); in tegra_dfll_runtime_resume()
411 clk_disable(td->ref_clk); in tegra_dfll_runtime_resume()
420 * tegra_dfll_runtime_suspend - disable all clocks needed by the DFLL
430 clk_disable(td->ref_clk); in tegra_dfll_runtime_suspend()
431 clk_disable(td->soc_clk); in tegra_dfll_runtime_suspend()
432 clk_disable(td->i2c_clk); in tegra_dfll_runtime_suspend()
439 * DFLL tuning operations (per-voltage-range tuning settings)
443 * dfll_tune_low - tune to DFLL and CPU settings valid for any voltage
447 * the low-voltage range. These settings are valid for any voltage,
452 td->tune_range = DFLL_TUNE_LOW; in dfll_tune_low()
454 dfll_writel(td, td->soc->cvb->cpu_dfll_data.tune0_low, DFLL_TUNE0); in dfll_tune_low()
455 dfll_writel(td, td->soc->cvb->cpu_dfll_data.tune1, DFLL_TUNE1); in dfll_tune_low()
458 if (td->soc->set_clock_trimmers_low) in dfll_tune_low()
459 td->soc->set_clock_trimmers_low(); in dfll_tune_low()
467 * dfll_scale_dvco_rate - calculate scaled rate from the DVCO rate
485 * dfll_set_mode - change the DFLL control mode
489 * Change the DFLL's operating mode between disabled, open-loop mode,
490 * and closed-loop mode, or vice versa.
495 td->mode = mode; in dfll_set_mode()
496 dfll_writel(td, mode - 1, DFLL_CTRL); in dfll_set_mode()
510 min_uv = td->lut_uv[out_min]; in get_dvco_rate_below()
512 opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate); in get_dvco_rate_below()
529 * DFLL-to-I2C controller interface
533 * dfll_i2c_set_output_enabled - enable/disable I2C PMIC voltage requests
559 * DFLL-to-PWM controller interface
563 * dfll_pwm_set_output_enabled - enable/disable PWM voltage requests
577 ret = pinctrl_select_state(td->pwm_pin, td->pwm_enable_state); in dfll_pwm_set_output_enabled()
579 dev_err(td->dev, "setting enable state failed\n"); in dfll_pwm_set_output_enabled()
580 return -EINVAL; in dfll_pwm_set_output_enabled()
584 div = DIV_ROUND_UP(td->ref_rate, td->pwm_rate); in dfll_pwm_set_output_enabled()
594 ret = pinctrl_select_state(td->pwm_pin, td->pwm_disable_state); in dfll_pwm_set_output_enabled()
596 dev_warn(td->dev, "setting disable state failed\n"); in dfll_pwm_set_output_enabled()
608 * dfll_set_force_output_value - set fixed value for force output
627 * dfll_set_force_output_enabled - enable/disable force output
647 * dfll_force_output - force output a fixed value
658 return -EINVAL; in dfll_force_output()
661 if ((td->mode < DFLL_CLOSED_LOOP) && in dfll_force_output()
670 * dfll_load_i2c_lut - load the voltage lookup table
673 * Load the voltage-to-PMIC register value lookup table into the DFLL
674 * IP block memory. Look-up tables can be loaded at any time.
682 if (i < td->lut_min) in dfll_load_i2c_lut()
683 lut_index = td->lut_min; in dfll_load_i2c_lut()
684 else if (i > td->lut_max) in dfll_load_i2c_lut()
685 lut_index = td->lut_max; in dfll_load_i2c_lut()
689 val = regulator_list_hardware_vsel(td->vdd_reg, in dfll_load_i2c_lut()
690 td->lut[lut_index]); in dfll_load_i2c_lut()
691 __raw_writel(val, td->lut_base + i * 4); in dfll_load_i2c_lut()
698 * dfll_init_i2c_if - set up the DFLL's DFLL-I2C interface
701 * During DFLL driver initialization, program the DFLL-I2C interface
704 * voltage-set commands, which are then passed to the DFLL's internal
711 if (td->i2c_slave_addr > 0x7f) { in dfll_init_i2c_if()
712 val = td->i2c_slave_addr << DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_10BIT; in dfll_init_i2c_if()
715 val = td->i2c_slave_addr << DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_7BIT; in dfll_init_i2c_if()
721 dfll_i2c_writel(td, td->i2c_reg, DFLL_I2C_VDD_REG_ADDR); in dfll_init_i2c_if()
723 val = DIV_ROUND_UP(td->i2c_clk_rate, td->i2c_fs_rate * 8); in dfll_init_i2c_if()
725 val = (val - 1) << DFLL_I2C_CLK_DIVISOR_FS_SHIFT; in dfll_init_i2c_if()
729 __raw_writel(val, td->i2c_controller_base + DFLL_I2C_CLK_DIVISOR); in dfll_init_i2c_if()
734 * dfll_init_out_if - prepare DFLL-to-PMIC interface
745 td->lut_min = td->lut_bottom; in dfll_init_out_if()
746 td->lut_max = td->lut_size - 1; in dfll_init_out_if()
747 td->lut_safe = td->lut_min + (td->lut_min < td->lut_max ? 1 : 0); in dfll_init_out_if()
753 val = (td->lut_safe << DFLL_OUTPUT_CFG_SAFE_SHIFT) | in dfll_init_out_if()
754 (td->lut_max << DFLL_OUTPUT_CFG_MAX_SHIFT) | in dfll_init_out_if()
755 (td->lut_min << DFLL_OUTPUT_CFG_MIN_SHIFT); in dfll_init_out_if()
764 if (td->pmu_if == TEGRA_DFLL_PMU_PWM) { in dfll_init_out_if()
765 u32 vinit = td->reg_init_uV; in dfll_init_out_if()
766 int vstep = td->soc->alignment.step_uv; in dfll_init_out_if()
767 unsigned long vmin = td->lut_uv[0]; in dfll_init_out_if()
773 vsel = DIV_ROUND_UP((vinit - vmin), vstep); in dfll_init_out_if()
787 * find_lut_index_for_rate - determine I2C LUT index for given DFLL rate
793 * to the integrator during rate changes. Returns -ENOENT if a suitable
801 opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate); in find_lut_index_for_rate()
805 align_step = dev_pm_opp_get_voltage(opp) / td->soc->alignment.step_uv; in find_lut_index_for_rate()
808 for (i = td->lut_bottom; i < td->lut_size; i++) { in find_lut_index_for_rate()
809 if ((td->lut_uv[i] / td->soc->alignment.step_uv) >= align_step) in find_lut_index_for_rate()
813 return -ENOENT; in find_lut_index_for_rate()
817 * dfll_calculate_rate_request - calculate DFLL parameters for a given rate
819 * @req: DFLL-rate-request structure
822 * Populate the DFLL-rate-request record @req fields with the scale_bits
824 * success, or -EINVAL if the requested rate in req->rate is too high
839 req->scale_bits = DFLL_FREQ_REQ_SCALE_MAX - 1; in dfll_calculate_rate_request()
840 if (rate < td->dvco_rate_min) { in dfll_calculate_rate_request()
844 td->dvco_rate_min / 1000); in dfll_calculate_rate_request()
846 dev_err(td->dev, "%s: Rate %lu is too low\n", in dfll_calculate_rate_request()
848 return -EINVAL; in dfll_calculate_rate_request()
850 req->scale_bits = scale - 1; in dfll_calculate_rate_request()
851 rate = td->dvco_rate_min; in dfll_calculate_rate_request()
855 val = DVCO_RATE_TO_MULT(rate, td->ref_rate); in dfll_calculate_rate_request()
857 dev_err(td->dev, "%s: Rate %lu is above dfll range\n", in dfll_calculate_rate_request()
859 return -EINVAL; in dfll_calculate_rate_request()
861 req->mult_bits = val; in dfll_calculate_rate_request()
862 req->dvco_target_rate = MULT_TO_DVCO_RATE(req->mult_bits, td->ref_rate); in dfll_calculate_rate_request()
863 req->rate = dfll_scale_dvco_rate(req->scale_bits, in dfll_calculate_rate_request()
864 req->dvco_target_rate); in dfll_calculate_rate_request()
865 req->lut_index = find_lut_index_for_rate(td, req->dvco_target_rate); in dfll_calculate_rate_request()
866 if (req->lut_index < 0) in dfll_calculate_rate_request()
867 return req->lut_index; in dfll_calculate_rate_request()
873 * dfll_set_frequency_request - start the frequency change operation
878 * frequency represented by @req. DFLL must be in closed-loop mode.
885 int coef = 128; /* FIXME: td->cg_scale? */; in dfll_set_frequency_request()
887 force_val = (req->lut_index - td->lut_safe) * coef / td->cg; in dfll_set_frequency_request()
890 val |= req->mult_bits << DFLL_FREQ_REQ_MULT_SHIFT; in dfll_set_frequency_request()
891 val |= req->scale_bits << DFLL_FREQ_REQ_SCALE_SHIFT; in dfll_set_frequency_request()
901 * dfll_request_rate - set the next rate for the DFLL to tune to
906 * settings. In closed-loop mode, update new settings immediately to
908 * until the next switch to closed loop. Returns 0 upon success,
909 * -EPERM if the DFLL driver has not yet been initialized, or -EINVAL
917 if (td->mode == DFLL_UNINITIALIZED) { in dfll_request_rate()
918 dev_err(td->dev, "%s: Cannot set DFLL rate in %s mode\n", in dfll_request_rate()
919 __func__, mode_name[td->mode]); in dfll_request_rate()
920 return -EPERM; in dfll_request_rate()
927 td->last_unrounded_rate = rate; in dfll_request_rate()
928 td->last_req = req; in dfll_request_rate()
930 if (td->mode == DFLL_CLOSED_LOOP) in dfll_request_rate()
931 dfll_set_frequency_request(td, &td->last_req); in dfll_request_rate()
937 * DFLL enable/disable & open-loop <-> closed-loop transitions
941 * dfll_disable - switch from open-loop mode to disabled mode
945 * or -EPERM if the DFLL is not currently in open-loop mode.
949 if (td->mode != DFLL_OPEN_LOOP) { in dfll_disable()
950 dev_err(td->dev, "cannot disable DFLL in %s mode\n", in dfll_disable()
951 mode_name[td->mode]); in dfll_disable()
952 return -EINVAL; in dfll_disable()
956 pm_runtime_put_sync(td->dev); in dfll_disable()
962 * dfll_enable - switch a disabled DFLL to open-loop mode
966 * or -EPERM if the DFLL is not currently disabled.
970 if (td->mode != DFLL_DISABLED) { in dfll_enable()
971 dev_err(td->dev, "cannot enable DFLL in %s mode\n", in dfll_enable()
972 mode_name[td->mode]); in dfll_enable()
973 return -EPERM; in dfll_enable()
976 pm_runtime_get_sync(td->dev); in dfll_enable()
983 * dfll_set_open_loop_config - prepare to switch to open-loop mode
986 * Prepare to switch the DFLL to open-loop mode. This switches the
987 * DFLL to the low-voltage tuning range, ensures that I2C output
989 * The DFLL's low-voltage tuning range parameters must be
997 /* always tune low (safe) in open loop */ in dfll_set_open_loop_config()
998 if (td->tune_range != DFLL_TUNE_LOW) in dfll_set_open_loop_config()
1009 * dfll_lock - switch from open-loop to closed-loop mode
1013 * -EINVAL if the DFLL's target rate hasn't been set yet, or -EPERM if the
1014 * DFLL is not currently in open-loop mode.
1018 struct dfll_rate_req *req = &td->last_req; in dfll_lock()
1020 switch (td->mode) { in dfll_lock()
1025 if (req->rate == 0) { in dfll_lock()
1026 dev_err(td->dev, "%s: Cannot lock DFLL at rate 0\n", in dfll_lock()
1028 return -EINVAL; in dfll_lock()
1031 if (td->pmu_if == TEGRA_DFLL_PMU_PWM) in dfll_lock()
1042 BUG_ON(td->mode > DFLL_CLOSED_LOOP); in dfll_lock()
1043 dev_err(td->dev, "%s: Cannot lock DFLL in %s mode\n", in dfll_lock()
1044 __func__, mode_name[td->mode]); in dfll_lock()
1045 return -EPERM; in dfll_lock()
1050 * dfll_unlock - switch from closed-loop to open-loop mode
1054 * or -EPERM if the DFLL is not currently in open-loop mode.
1058 switch (td->mode) { in dfll_unlock()
1062 if (td->pmu_if == TEGRA_DFLL_PMU_PWM) in dfll_unlock()
1072 BUG_ON(td->mode > DFLL_CLOSED_LOOP); in dfll_unlock()
1073 dev_err(td->dev, "%s: Cannot unlock DFLL in %s mode\n", in dfll_unlock()
1074 __func__, mode_name[td->mode]); in dfll_unlock()
1075 return -EPERM; in dfll_unlock()
1082 * When the DFLL is being controlled by the CCF, always enter closed loop
1126 return td->last_unrounded_rate; in dfll_clk_recalc_rate()
1129 /* Must use determine_rate since it allows for rates exceeding 2^31-1 */
1137 ret = dfll_calculate_rate_request(td, &req, clk_req->rate); in dfll_clk_determine_rate()
1173 * dfll_register_clk - register the DFLL output clock with the clock framework
1177 * the DFLL driver as an OF clock provider. Returns 0 upon success or -EINVAL
1178 * or -ENOMEM upon failure.
1184 dfll_clk_init_data.name = td->output_clock_name; in dfll_register_clk()
1185 td->dfll_clk_hw.init = &dfll_clk_init_data; in dfll_register_clk()
1187 td->dfll_clk = clk_register(td->dev, &td->dfll_clk_hw); in dfll_register_clk()
1188 if (IS_ERR(td->dfll_clk)) { in dfll_register_clk()
1189 dev_err(td->dev, "DFLL clock registration error\n"); in dfll_register_clk()
1190 return -EINVAL; in dfll_register_clk()
1193 ret = of_clk_add_provider(td->dev->of_node, of_clk_src_simple_get, in dfll_register_clk()
1194 td->dfll_clk); in dfll_register_clk()
1196 dev_err(td->dev, "of_clk_add_provider() failed\n"); in dfll_register_clk()
1198 clk_unregister(td->dfll_clk); in dfll_register_clk()
1206 * dfll_unregister_clk - unregister the DFLL output clock
1214 of_clk_del_provider(td->dev->of_node); in dfll_unregister_clk()
1215 clk_unregister(td->dfll_clk); in dfll_unregister_clk()
1216 td->dfll_clk = NULL; in dfll_unregister_clk()
1229 * dfll_calc_monitored_rate - convert DFLL_MONITOR_DATA_VAL rate into real freq
1243 * dfll_read_monitor_rate - return the DFLL's output rate from internal monitor
1247 * internal monitoring hardware. This works in both open-loop and
1248 * closed-loop mode, and takes the output scaler setting into account.
1265 pre_scaler_rate = dfll_calc_monitored_rate(v, td->ref_rate); in dfll_read_monitor_rate()
1295 *val = (td->mode == DFLL_CLOSED_LOOP); in attr_lock_get()
1327 struct tegra_dfll *td = s->private; in attr_registers_show()
1346 if (td->pmu_if == TEGRA_DFLL_PMU_I2C) { in attr_registers_show()
1350 __raw_readl(td->i2c_controller_base + offs)); in attr_registers_show()
1355 __raw_readl(td->lut_base + offs)); in attr_registers_show()
1367 if (!td || (td->mode == DFLL_UNINITIALIZED)) in dfll_debug_init()
1371 td->debugfs_dir = root; in dfll_debug_init()
1389 * dfll_set_default_params - program non-output related DFLL parameters
1393 * program parameters for the closed loop integrator, DVCO tuning,
1400 val = DIV_ROUND_UP(td->ref_rate, td->sample_rate * 32); in dfll_set_default_params()
1404 val = (td->force_mode << DFLL_PARAMS_FORCE_MODE_SHIFT) | in dfll_set_default_params()
1405 (td->cf << DFLL_PARAMS_CF_PARAM_SHIFT) | in dfll_set_default_params()
1406 (td->ci << DFLL_PARAMS_CI_PARAM_SHIFT) | in dfll_set_default_params()
1407 (td->cg << DFLL_PARAMS_CG_PARAM_SHIFT) | in dfll_set_default_params()
1408 (td->cg_scale ? DFLL_PARAMS_CG_SCALE : 0); in dfll_set_default_params()
1412 dfll_writel(td, td->droop_ctrl, DFLL_DROOP_CTRL); in dfll_set_default_params()
1417 * dfll_init_clks - clk_get() the DFLL source clocks
1426 td->ref_clk = devm_clk_get(td->dev, "ref"); in dfll_init_clks()
1427 if (IS_ERR(td->ref_clk)) { in dfll_init_clks()
1428 dev_err(td->dev, "missing ref clock\n"); in dfll_init_clks()
1429 return PTR_ERR(td->ref_clk); in dfll_init_clks()
1432 td->soc_clk = devm_clk_get(td->dev, "soc"); in dfll_init_clks()
1433 if (IS_ERR(td->soc_clk)) { in dfll_init_clks()
1434 dev_err(td->dev, "missing soc clock\n"); in dfll_init_clks()
1435 return PTR_ERR(td->soc_clk); in dfll_init_clks()
1438 td->i2c_clk = devm_clk_get(td->dev, "i2c"); in dfll_init_clks()
1439 if (IS_ERR(td->i2c_clk)) { in dfll_init_clks()
1440 dev_err(td->dev, "missing i2c clock\n"); in dfll_init_clks()
1441 return PTR_ERR(td->i2c_clk); in dfll_init_clks()
1443 td->i2c_clk_rate = clk_get_rate(td->i2c_clk); in dfll_init_clks()
1449 * dfll_init - Prepare the DFLL IP block for use
1461 td->ref_rate = clk_get_rate(td->ref_clk); in dfll_init()
1462 if (td->ref_rate != REF_CLOCK_RATE) { in dfll_init()
1463 dev_err(td->dev, "unexpected ref clk rate %lu, expecting %lu", in dfll_init()
1464 td->ref_rate, REF_CLOCK_RATE); in dfll_init()
1465 return -EINVAL; in dfll_init()
1468 reset_control_deassert(td->dfll_rst); in dfll_init()
1469 reset_control_deassert(td->dvco_rst); in dfll_init()
1471 ret = clk_prepare(td->ref_clk); in dfll_init()
1473 dev_err(td->dev, "failed to prepare ref_clk\n"); in dfll_init()
1477 ret = clk_prepare(td->soc_clk); in dfll_init()
1479 dev_err(td->dev, "failed to prepare soc_clk\n"); in dfll_init()
1483 ret = clk_prepare(td->i2c_clk); in dfll_init()
1485 dev_err(td->dev, "failed to prepare i2c_clk\n"); in dfll_init()
1489 td->last_unrounded_rate = 0; in dfll_init()
1491 pm_runtime_enable(td->dev); in dfll_init()
1492 pm_runtime_get_sync(td->dev); in dfll_init()
1497 if (td->soc->init_clock_trimmers) in dfll_init()
1498 td->soc->init_clock_trimmers(); in dfll_init()
1504 pm_runtime_put_sync(td->dev); in dfll_init()
1509 clk_unprepare(td->soc_clk); in dfll_init()
1511 clk_unprepare(td->ref_clk); in dfll_init()
1513 reset_control_assert(td->dvco_rst); in dfll_init()
1514 reset_control_assert(td->dfll_rst); in dfll_init()
1520 * tegra_dfll_suspend - check DFLL is disabled
1531 dev_err(td->dev, "DFLL still enabled while suspending\n"); in tegra_dfll_suspend()
1532 return -EBUSY; in tegra_dfll_suspend()
1535 reset_control_assert(td->dvco_rst); in tegra_dfll_suspend()
1536 reset_control_assert(td->dfll_rst); in tegra_dfll_suspend()
1543 * tegra_dfll_resume - reinitialize DFLL on resume
1548 * DFLL clock is enabled later in closed loop mode by CPUFreq
1555 reset_control_deassert(td->dfll_rst); in tegra_dfll_resume()
1556 reset_control_deassert(td->dvco_rst); in tegra_dfll_resume()
1558 pm_runtime_get_sync(td->dev); in tegra_dfll_resume()
1563 if (td->soc->init_clock_trimmers) in tegra_dfll_resume()
1564 td->soc->init_clock_trimmers(); in tegra_dfll_resume()
1570 pm_runtime_put_sync(td->dev); in tegra_dfll_resume()
1581 * Find a PMIC voltage register-to-voltage mapping for the given voltage.
1588 if (WARN_ON(td->pmu_if == TEGRA_DFLL_PMU_PWM)) in find_vdd_map_entry_exact()
1589 return -EINVAL; in find_vdd_map_entry_exact()
1591 align_step = uV / td->soc->alignment.step_uv; in find_vdd_map_entry_exact()
1592 n_voltages = regulator_count_voltages(td->vdd_reg); in find_vdd_map_entry_exact()
1594 reg_uV = regulator_list_voltage(td->vdd_reg, i); in find_vdd_map_entry_exact()
1598 reg_volt_id = reg_uV / td->soc->alignment.step_uv; in find_vdd_map_entry_exact()
1604 dev_err(td->dev, "no voltage map entry for %d uV\n", uV); in find_vdd_map_entry_exact()
1605 return -EINVAL; in find_vdd_map_entry_exact()
1609 * Find a PMIC voltage register-to-voltage mapping for the given voltage,
1616 if (WARN_ON(td->pmu_if == TEGRA_DFLL_PMU_PWM)) in find_vdd_map_entry_min()
1617 return -EINVAL; in find_vdd_map_entry_min()
1619 align_step = uV / td->soc->alignment.step_uv; in find_vdd_map_entry_min()
1620 n_voltages = regulator_count_voltages(td->vdd_reg); in find_vdd_map_entry_min()
1622 reg_uV = regulator_list_voltage(td->vdd_reg, i); in find_vdd_map_entry_min()
1626 reg_volt_id = reg_uV / td->soc->alignment.step_uv; in find_vdd_map_entry_min()
1632 dev_err(td->dev, "no voltage map entry rounding to %d uV\n", uV); in find_vdd_map_entry_min()
1633 return -EINVAL; in find_vdd_map_entry_min()
1637 * dfll_build_pwm_lut - build the PWM regulator lookup table
1641 * Look-up table in h/w is ignored when PWM is used as DFLL interface to PMIC.
1642 * In this case closed loop output is controlling duty cycle directly. The s/w
1643 * look-up that maps PWM duty cycle to voltage is still built by this function.
1650 int v_min = td->soc->cvb->min_millivolts * 1000; in dfll_build_pwm_lut()
1653 reg_volt = td->lut_uv[i]; in dfll_build_pwm_lut()
1660 td->lut[i] = i; in dfll_build_pwm_lut()
1666 td->lut_size = i; in dfll_build_pwm_lut()
1668 (lut_bottom + 1 >= td->lut_size)) { in dfll_build_pwm_lut()
1669 dev_err(td->dev, "no voltage above DFLL minimum %d mV\n", in dfll_build_pwm_lut()
1670 td->soc->cvb->min_millivolts); in dfll_build_pwm_lut()
1671 return -EINVAL; in dfll_build_pwm_lut()
1673 td->lut_bottom = lut_bottom; in dfll_build_pwm_lut()
1676 rate = get_dvco_rate_below(td, td->lut_bottom); in dfll_build_pwm_lut()
1678 dev_err(td->dev, "no opp below DFLL minimum voltage %d mV\n", in dfll_build_pwm_lut()
1679 td->soc->cvb->min_millivolts); in dfll_build_pwm_lut()
1680 return -EINVAL; in dfll_build_pwm_lut()
1682 td->dvco_rate_min = rate; in dfll_build_pwm_lut()
1688 * dfll_build_i2c_lut - build the I2C voltage register lookup table
1692 * The DFLL hardware has 33 bytes of look-up table RAM that must be filled with
1694 * This function builds the look-up table based on the OPP table provided by
1695 * the soc-specific platform driver (td->soc->opp_dev) and the PMIC
1696 * register-to-voltage mapping queried from the regulator framework.
1698 * On success, fills in td->lut and returns 0, or -err on failure.
1703 int ret = -EINVAL; in dfll_build_i2c_lut()
1706 v = td->soc->cvb->min_millivolts * 1000; in dfll_build_i2c_lut()
1710 td->lut[0] = lut; in dfll_build_i2c_lut()
1711 td->lut_bottom = 0; in dfll_build_i2c_lut()
1716 opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate); in dfll_build_i2c_lut()
1721 if (v_opp <= td->soc->cvb->min_millivolts * 1000) in dfll_build_i2c_lut()
1722 td->dvco_rate_min = dev_pm_opp_get_freq(opp); in dfll_build_i2c_lut()
1727 v += max(1UL, (v_max - v) / (MAX_DFLL_VOLTAGES - j)); in dfll_build_i2c_lut()
1734 if (selector != td->lut[j - 1]) in dfll_build_i2c_lut()
1735 td->lut[j++] = selector; in dfll_build_i2c_lut()
1738 v = (j == MAX_DFLL_VOLTAGES - 1) ? v_max : v_opp; in dfll_build_i2c_lut()
1742 if (selector != td->lut[j - 1]) in dfll_build_i2c_lut()
1743 td->lut[j++] = selector; in dfll_build_i2c_lut()
1748 td->lut_size = j; in dfll_build_i2c_lut()
1750 if (!td->dvco_rate_min) in dfll_build_i2c_lut()
1751 dev_err(td->dev, "no opp above DFLL minimum voltage %d mV\n", in dfll_build_i2c_lut()
1752 td->soc->cvb->min_millivolts); in dfll_build_i2c_lut()
1755 for (j = 0; j < td->lut_size; j++) in dfll_build_i2c_lut()
1756 td->lut_uv[j] = in dfll_build_i2c_lut()
1757 regulator_list_voltage(td->vdd_reg, in dfll_build_i2c_lut()
1758 td->lut[j]); in dfll_build_i2c_lut()
1771 opp = dev_pm_opp_find_freq_floor(td->soc->dev, &rate); in dfll_build_lut()
1773 dev_err(td->dev, "couldn't get vmax opp, empty opp table?\n"); in dfll_build_lut()
1774 return -EINVAL; in dfll_build_lut()
1779 if (td->pmu_if == TEGRA_DFLL_PMU_PWM) in dfll_build_lut()
1786 * read_dt_param - helper function for reading required parameters from the DT
1797 int err = of_property_read_u32(td->dev->of_node, param, dest); in read_dt_param()
1800 dev_err(td->dev, "failed to read DT parameter %s: %d\n", in read_dt_param()
1809 * dfll_fetch_i2c_params - query PMIC I2C params from DT & regulator subsystem
1814 * Returns 0 on success or -err on failure.
1824 if (!read_dt_param(td, "nvidia,i2c-fs-rate", &td->i2c_fs_rate)) in dfll_fetch_i2c_params()
1825 return -EINVAL; in dfll_fetch_i2c_params()
1827 regmap = regulator_get_regmap(td->vdd_reg); in dfll_fetch_i2c_params()
1831 td->i2c_slave_addr = i2c_client->addr; in dfll_fetch_i2c_params()
1833 ret = regulator_get_hardware_vsel_register(td->vdd_reg, in dfll_fetch_i2c_params()
1837 dev_err(td->dev, in dfll_fetch_i2c_params()
1839 return -EINVAL; in dfll_fetch_i2c_params()
1841 td->i2c_reg = vsel_reg; in dfll_fetch_i2c_params()
1851 if (!td->soc->alignment.step_uv || !td->soc->alignment.offset_uv) { in dfll_fetch_pwm_params()
1852 dev_err(td->dev, in dfll_fetch_pwm_params()
1854 return -EINVAL; in dfll_fetch_pwm_params()
1857 td->lut_uv[i] = td->soc->alignment.offset_uv + in dfll_fetch_pwm_params()
1858 i * td->soc->alignment.step_uv; in dfll_fetch_pwm_params()
1860 ret = read_dt_param(td, "nvidia,pwm-tristate-microvolts", in dfll_fetch_pwm_params()
1861 &td->reg_init_uV); in dfll_fetch_pwm_params()
1863 dev_err(td->dev, "couldn't get initialized voltage\n"); in dfll_fetch_pwm_params()
1864 return -EINVAL; in dfll_fetch_pwm_params()
1867 ret = read_dt_param(td, "nvidia,pwm-period-nanoseconds", &pwm_period); in dfll_fetch_pwm_params()
1869 dev_err(td->dev, "couldn't get PWM period\n"); in dfll_fetch_pwm_params()
1870 return -EINVAL; in dfll_fetch_pwm_params()
1872 td->pwm_rate = (NSEC_PER_SEC / pwm_period) * (MAX_DFLL_VOLTAGES - 1); in dfll_fetch_pwm_params()
1874 td->pwm_pin = devm_pinctrl_get(td->dev); in dfll_fetch_pwm_params()
1875 if (IS_ERR(td->pwm_pin)) { in dfll_fetch_pwm_params()
1876 dev_err(td->dev, "DT: missing pinctrl device\n"); in dfll_fetch_pwm_params()
1877 return PTR_ERR(td->pwm_pin); in dfll_fetch_pwm_params()
1880 td->pwm_enable_state = pinctrl_lookup_state(td->pwm_pin, in dfll_fetch_pwm_params()
1882 if (IS_ERR(td->pwm_enable_state)) { in dfll_fetch_pwm_params()
1883 dev_err(td->dev, "DT: missing pwm enabled state\n"); in dfll_fetch_pwm_params()
1884 return PTR_ERR(td->pwm_enable_state); in dfll_fetch_pwm_params()
1887 td->pwm_disable_state = pinctrl_lookup_state(td->pwm_pin, in dfll_fetch_pwm_params()
1889 if (IS_ERR(td->pwm_disable_state)) { in dfll_fetch_pwm_params()
1890 dev_err(td->dev, "DT: missing pwm disabled state\n"); in dfll_fetch_pwm_params()
1891 return PTR_ERR(td->pwm_disable_state); in dfll_fetch_pwm_params()
1898 * dfll_fetch_common_params - read DFLL parameters from the device tree
1902 * Returns 0 on success or -EINVAL on any failure.
1908 ok &= read_dt_param(td, "nvidia,droop-ctrl", &td->droop_ctrl); in dfll_fetch_common_params()
1909 ok &= read_dt_param(td, "nvidia,sample-rate", &td->sample_rate); in dfll_fetch_common_params()
1910 ok &= read_dt_param(td, "nvidia,force-mode", &td->force_mode); in dfll_fetch_common_params()
1911 ok &= read_dt_param(td, "nvidia,cf", &td->cf); in dfll_fetch_common_params()
1912 ok &= read_dt_param(td, "nvidia,ci", &td->ci); in dfll_fetch_common_params()
1913 ok &= read_dt_param(td, "nvidia,cg", &td->cg); in dfll_fetch_common_params()
1914 td->cg_scale = of_property_read_bool(td->dev->of_node, in dfll_fetch_common_params()
1915 "nvidia,cg-scale"); in dfll_fetch_common_params()
1917 if (of_property_read_string(td->dev->of_node, "clock-output-names", in dfll_fetch_common_params()
1918 &td->output_clock_name)) { in dfll_fetch_common_params()
1919 dev_err(td->dev, "missing clock-output-names property\n"); in dfll_fetch_common_params()
1923 return ok ? 0 : -EINVAL; in dfll_fetch_common_params()
1927 * API exported to per-SoC platform drivers
1931 * tegra_dfll_register - probe a Tegra DFLL device
1933 * @soc: Per-SoC integration and characterization data for this DFLL instance
1936 * by a SoC-specific shim driver that passes in per-SoC integration
1937 * and configuration data via @soc. Returns 0 on success or -err on failure.
1947 dev_err(&pdev->dev, "no tegra_dfll_soc_data provided\n"); in tegra_dfll_register()
1948 return -EINVAL; in tegra_dfll_register()
1951 td = devm_kzalloc(&pdev->dev, sizeof(*td), GFP_KERNEL); in tegra_dfll_register()
1953 return -ENOMEM; in tegra_dfll_register()
1954 td->dev = &pdev->dev; in tegra_dfll_register()
1957 td->soc = soc; in tegra_dfll_register()
1959 td->dfll_rst = devm_reset_control_get_optional(td->dev, "dfll"); in tegra_dfll_register()
1960 if (IS_ERR(td->dfll_rst)) { in tegra_dfll_register()
1961 dev_err(td->dev, "couldn't get dfll reset\n"); in tegra_dfll_register()
1962 return PTR_ERR(td->dfll_rst); in tegra_dfll_register()
1965 td->dvco_rst = devm_reset_control_get(td->dev, "dvco"); in tegra_dfll_register()
1966 if (IS_ERR(td->dvco_rst)) { in tegra_dfll_register()
1967 dev_err(td->dev, "couldn't get dvco reset\n"); in tegra_dfll_register()
1968 return PTR_ERR(td->dvco_rst); in tegra_dfll_register()
1973 dev_err(td->dev, "couldn't parse device tree parameters\n"); in tegra_dfll_register()
1977 if (of_property_read_bool(td->dev->of_node, "nvidia,pwm-to-pmic")) { in tegra_dfll_register()
1978 td->pmu_if = TEGRA_DFLL_PMU_PWM; in tegra_dfll_register()
1981 td->vdd_reg = devm_regulator_get(td->dev, "vdd-cpu"); in tegra_dfll_register()
1982 if (IS_ERR(td->vdd_reg)) { in tegra_dfll_register()
1983 dev_err(td->dev, "couldn't get vdd_cpu regulator\n"); in tegra_dfll_register()
1984 return PTR_ERR(td->vdd_reg); in tegra_dfll_register()
1986 td->pmu_if = TEGRA_DFLL_PMU_I2C; in tegra_dfll_register()
1994 dev_err(td->dev, "couldn't build LUT\n"); in tegra_dfll_register()
2000 dev_err(td->dev, "no control register resource\n"); in tegra_dfll_register()
2001 return -ENODEV; in tegra_dfll_register()
2004 td->base = devm_ioremap(td->dev, mem->start, resource_size(mem)); in tegra_dfll_register()
2005 if (!td->base) { in tegra_dfll_register()
2006 dev_err(td->dev, "couldn't ioremap DFLL control registers\n"); in tegra_dfll_register()
2007 return -ENODEV; in tegra_dfll_register()
2012 dev_err(td->dev, "no i2c_base resource\n"); in tegra_dfll_register()
2013 return -ENODEV; in tegra_dfll_register()
2016 td->i2c_base = devm_ioremap(td->dev, mem->start, resource_size(mem)); in tegra_dfll_register()
2017 if (!td->i2c_base) { in tegra_dfll_register()
2018 dev_err(td->dev, "couldn't ioremap i2c_base resource\n"); in tegra_dfll_register()
2019 return -ENODEV; in tegra_dfll_register()
2024 dev_err(td->dev, "no i2c_controller_base resource\n"); in tegra_dfll_register()
2025 return -ENODEV; in tegra_dfll_register()
2028 td->i2c_controller_base = devm_ioremap(td->dev, mem->start, in tegra_dfll_register()
2030 if (!td->i2c_controller_base) { in tegra_dfll_register()
2031 dev_err(td->dev, in tegra_dfll_register()
2033 return -ENODEV; in tegra_dfll_register()
2038 dev_err(td->dev, "no lut_base resource\n"); in tegra_dfll_register()
2039 return -ENODEV; in tegra_dfll_register()
2042 td->lut_base = devm_ioremap(td->dev, mem->start, resource_size(mem)); in tegra_dfll_register()
2043 if (!td->lut_base) { in tegra_dfll_register()
2044 dev_err(td->dev, in tegra_dfll_register()
2046 return -ENODEV; in tegra_dfll_register()
2051 dev_err(&pdev->dev, "DFLL clock init error\n"); in tegra_dfll_register()
2062 dev_err(&pdev->dev, "DFLL clk registration failed\n"); in tegra_dfll_register()
2073 * tegra_dfll_unregister - release all of the DFLL driver resources for a device
2078 * soc pointer upon success or -EBUSY if the DFLL is still active.
2088 if (td->mode != DFLL_DISABLED) { in tegra_dfll_unregister()
2089 dev_err(&pdev->dev, in tegra_dfll_unregister()
2091 return ERR_PTR(-EBUSY); in tegra_dfll_unregister()
2094 debugfs_remove_recursive(td->debugfs_dir); in tegra_dfll_unregister()
2097 pm_runtime_disable(&pdev->dev); in tegra_dfll_unregister()
2099 clk_unprepare(td->ref_clk); in tegra_dfll_unregister()
2100 clk_unprepare(td->soc_clk); in tegra_dfll_unregister()
2101 clk_unprepare(td->i2c_clk); in tegra_dfll_unregister()
2103 reset_control_assert(td->dvco_rst); in tegra_dfll_unregister()
2104 reset_control_assert(td->dfll_rst); in tegra_dfll_unregister()
2106 return td->soc; in tegra_dfll_unregister()