1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
15 #include "clk-factors.h"
18  * sun4i_a10_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
27 	/* These clocks can only divide, so we will never be able to achieve  in sun4i_a10_get_mod0_factors()
29 	if (req->rate > req->parent_rate)  in sun4i_a10_get_mod0_factors()
30 		req->rate = req->parent_rate;  in sun4i_a10_get_mod0_factors()
32 	div = DIV_ROUND_UP(req->parent_rate, req->rate);  in sun4i_a10_get_mod0_factors()
45 	req->rate = (req->parent_rate >> calcp) / calcm;  in sun4i_a10_get_mod0_factors()
46 	req->m = calcm - 1;  in sun4i_a10_get_mod0_factors()
47 	req->p = calcp;  in sun4i_a10_get_mod0_factors()
85 CLK_OF_DECLARE_DRIVER(sun4i_a10_mod0, "allwinner,sun4i-a10-mod0-clk",
90 	struct device_node *np = pdev->dev.of_node;  in sun4i_a10_mod0_clk_probe()
94 		return -ENODEV;  in sun4i_a10_mod0_clk_probe()
106 	{ .compatible = "allwinner,sun4i-a10-mod0-clk" },
112 		.name = "sun4i-a10-mod0-clk",
133 		pr_err("Could not get registers for mod0-clk: %pOFn\n",  in sun9i_a80_mod0_setup()
141 CLK_OF_DECLARE(sun9i_a80_mod0, "allwinner,sun9i-a80-mod0-clk", sun9i_a80_mod0_setup);
151 		pr_err("Could not get registers for a13-mbus-clk\n");  in sun5i_a13_mbus_setup()
159 CLK_OF_DECLARE(sun5i_a13_mbus, "allwinner,sun5i-a13-mbus-clk", sun5i_a13_mbus_setup);
172 	struct clk *mmc, *mmc_parent, *clk = hw->clk;  in mmc_get_phase()
179 	value = readl(phase->reg);  in mmc_get_phase()
180 	delay = (value >> phase->offset) & 0x3;  in mmc_get_phase()
188 		return -EINVAL;  in mmc_get_phase()
193 		return -EINVAL;  in mmc_get_phase()
198 		return -EINVAL;  in mmc_get_phase()
203 		return -EINVAL;  in mmc_get_phase()
214 	struct clk *mmc, *mmc_parent, *clk = hw->clk;  in mmc_set_phase()
224 		return -EINVAL;  in mmc_set_phase()
229 		return -EINVAL;  in mmc_set_phase()
234 		return -EINVAL;  in mmc_set_phase()
239 		return -EINVAL;  in mmc_set_phase()
248 		 * We can only outphase the clocks by multiple of the  in mmc_set_phase()
255 		 * If we simplify this formula, we can see that the  in mmc_set_phase()
266 	spin_lock_irqsave(phase->lock, flags);  in mmc_set_phase()
267 	value = readl(phase->reg);  in mmc_set_phase()
268 	value &= ~GENMASK(phase->offset + 3, phase->offset);  in mmc_set_phase()
269 	value |= delay << phase->offset;  in mmc_set_phase()
270 	writel(value, phase->reg);  in mmc_set_phase()
271 	spin_unlock_irqrestore(phase->lock, flags);  in mmc_set_phase()
282  * sunxi_mmc_setup - Common setup function for mmc module clocks
307 	clk_data->clks = kcalloc(3, sizeof(*clk_data->clks), GFP_KERNEL);  in sunxi_mmc_setup()
308 	if (!clk_data->clks)  in sunxi_mmc_setup()
311 	clk_data->clk_num = 3;  in sunxi_mmc_setup()
312 	clk_data->clks[0] = sunxi_factors_register(node, data, lock, reg);  in sunxi_mmc_setup()
313 	if (!clk_data->clks[0])  in sunxi_mmc_setup()
316 	parent = __clk_get_name(clk_data->clks[0]);  in sunxi_mmc_setup()
330 		phase->hw.init = &init;  in sunxi_mmc_setup()
331 		phase->reg = reg;  in sunxi_mmc_setup()
332 		phase->lock = lock;  in sunxi_mmc_setup()
335 			phase->offset = 8;  in sunxi_mmc_setup()
337 			phase->offset = 20;  in sunxi_mmc_setup()
339 		if (of_property_read_string_index(node, "clock-output-names",  in sunxi_mmc_setup()
341 			init.name = node->name;  in sunxi_mmc_setup()
343 		clk_data->clks[i] = clk_register(NULL, &phase->hw);  in sunxi_mmc_setup()
344 		if (IS_ERR(clk_data->clks[i])) {  in sunxi_mmc_setup()
355 	kfree(clk_data->clks);  in sunxi_mmc_setup()
366 CLK_OF_DECLARE(sun4i_a10_mmc, "allwinner,sun4i-a10-mmc-clk", sun4i_a10_mmc_setup);
374 CLK_OF_DECLARE(sun9i_a80_mmc, "allwinner,sun9i-a80-mmc-clk", sun9i_a80_mmc_setup);