1 // SPDX-License-Identifier: GPL-2.0-or-later
4  * Maxime Ripard <maxime.ripard@free-electrons.com>
7 #include <linux/clk-provider.h>
36 			if ((rate - tmp_rate) < (rate - best_rate)) {  in ccu_mp_find_best()
117 	if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)  in ccu_mp_round_rate()
118 		rate *= cmp->fixed_post_div;  in ccu_mp_round_rate()
120 	if (cmp->common.features & CCU_FEATURE_DUAL_DIV)  in ccu_mp_round_rate()
123 	max_m = cmp->m.max ?: 1 << cmp->m.width;  in ccu_mp_round_rate()
125 		max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);  in ccu_mp_round_rate()
127 		max_p = cmp->p.max ?: 1 << cmp->p.width;  in ccu_mp_round_rate()
129 	if (!clk_hw_can_set_rate_parent(&cmp->common.hw)) {  in ccu_mp_round_rate()
137 	if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)  in ccu_mp_round_rate()
138 		rate /= cmp->fixed_post_div;  in ccu_mp_round_rate()
147 	return ccu_gate_helper_disable(&cmp->common, cmp->enable);  in ccu_mp_disable()
154 	return ccu_gate_helper_enable(&cmp->common, cmp->enable);  in ccu_mp_enable()
161 	return ccu_gate_helper_is_enabled(&cmp->common, cmp->enable);  in ccu_mp_is_enabled()
172 	/* Adjust parent_rate according to pre-dividers */  in ccu_mp_recalc_rate()
173 	parent_rate = ccu_mux_helper_apply_prediv(&cmp->common, &cmp->mux, -1,  in ccu_mp_recalc_rate()
176 	reg = readl(cmp->common.base + cmp->common.reg);  in ccu_mp_recalc_rate()
178 	m = reg >> cmp->m.shift;  in ccu_mp_recalc_rate()
179 	m &= (1 << cmp->m.width) - 1;  in ccu_mp_recalc_rate()
180 	m += cmp->m.offset;  in ccu_mp_recalc_rate()
184 	p = reg >> cmp->p.shift;  in ccu_mp_recalc_rate()
185 	p &= (1 << cmp->p.width) - 1;  in ccu_mp_recalc_rate()
187 	if (cmp->common.features & CCU_FEATURE_DUAL_DIV)  in ccu_mp_recalc_rate()
188 		rate = (parent_rate / (p + cmp->p.offset)) / m;  in ccu_mp_recalc_rate()
192 	if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)  in ccu_mp_recalc_rate()
193 		rate /= cmp->fixed_post_div;  in ccu_mp_recalc_rate()
203 	return ccu_mux_helper_determine_rate(&cmp->common, &cmp->mux,  in ccu_mp_determine_rate()
217 	if (cmp->common.features & CCU_FEATURE_DUAL_DIV)  in ccu_mp_set_rate()
220 	/* Adjust parent_rate according to pre-dividers */  in ccu_mp_set_rate()
221 	parent_rate = ccu_mux_helper_apply_prediv(&cmp->common, &cmp->mux, -1,  in ccu_mp_set_rate()
224 	max_m = cmp->m.max ?: 1 << cmp->m.width;  in ccu_mp_set_rate()
226 		max_p = cmp->p.max ?: 1 << ((1 << cmp->p.width) - 1);  in ccu_mp_set_rate()
228 		max_p = cmp->p.max ?: 1 << cmp->p.width;  in ccu_mp_set_rate()
230 	/* Adjust target rate according to post-dividers */  in ccu_mp_set_rate()
231 	if (cmp->common.features & CCU_FEATURE_FIXED_POSTDIV)  in ccu_mp_set_rate()
232 		rate = rate * cmp->fixed_post_div;  in ccu_mp_set_rate()
236 	spin_lock_irqsave(cmp->common.lock, flags);  in ccu_mp_set_rate()
238 	reg = readl(cmp->common.base + cmp->common.reg);  in ccu_mp_set_rate()
239 	reg &= ~GENMASK(cmp->m.width + cmp->m.shift - 1, cmp->m.shift);  in ccu_mp_set_rate()
240 	reg &= ~GENMASK(cmp->p.width + cmp->p.shift - 1, cmp->p.shift);  in ccu_mp_set_rate()
241 	reg |= (m - cmp->m.offset) << cmp->m.shift;  in ccu_mp_set_rate()
243 		reg |= ilog2(p) << cmp->p.shift;  in ccu_mp_set_rate()
245 		reg |= (p - cmp->p.offset) << cmp->p.shift;  in ccu_mp_set_rate()
247 	writel(reg, cmp->common.base + cmp->common.reg);  in ccu_mp_set_rate()
249 	spin_unlock_irqrestore(cmp->common.lock, flags);  in ccu_mp_set_rate()
258 	return ccu_mux_helper_get_parent(&cmp->common, &cmp->mux);  in ccu_mp_get_parent()
265 	return ccu_mux_helper_set_parent(&cmp->common, &cmp->mux, index);  in ccu_mp_set_parent()
283  * Support for MMC timing mode switching
287  * and set the timing mode on supported SoCs.
290  * takes in to account the timing mode switch. When the new timing
291  * mode is active, the clock output rate is halved. This new class
294  * if the new timing mode bit is set, to account for the post
296  * are halved if the mode bit is set.
304 	u32 val = readl(cm->base + cm->reg);  in ccu_mp_mmc_recalc_rate()
315 	u32 val = readl(cm->base + cm->reg);  in ccu_mp_mmc_determine_rate()
320 		req->rate *= 2;  in ccu_mp_mmc_determine_rate()
321 		req->min_rate *= 2;  in ccu_mp_mmc_determine_rate()
322 		req->max_rate *= 2;  in ccu_mp_mmc_determine_rate()
327 	/* re-adjust the requested clock rate back */  in ccu_mp_mmc_determine_rate()
329 		req->rate /= 2;  in ccu_mp_mmc_determine_rate()
330 		req->min_rate /= 2;  in ccu_mp_mmc_determine_rate()
331 		req->max_rate /= 2;  in ccu_mp_mmc_determine_rate()
341 	u32 val = readl(cm->base + cm->reg);  in ccu_mp_mmc_set_rate()