Lines Matching +full:0 +full:x2d0
33 .m = _SUNXI_CCU_DIV(0, 2),
38 .reg = 0x000,
53 #define SUNIV_PLL_AUDIO_REG 0x008
56 "osc24M", 0x008,
58 0, 5, /* M */
64 "osc24M", 0x010,
66 0, 4, /* M */
69 270000000, /* frac rate 0 */
76 "osc24M", 0x018,
78 0, 4, /* M */
81 270000000, /* frac rate 0 */
88 "osc24M", 0x020,
91 0, 2, /* M */
102 .reg = 0x028,
104 &ccu_nk_ops, 0),
111 0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
130 .reg = 0x054,
135 0),
140 { .val = 0, .div = 2 },
147 0x054, 8, 2, apb_div_table, 0);
150 0x060, BIT(6), 0);
152 0x060, BIT(8), 0);
154 0x060, BIT(9), 0);
156 0x060, BIT(14), 0);
158 0x060, BIT(20), 0);
160 0x060, BIT(21), 0);
162 0x060, BIT(24), 0);
165 0x064, BIT(0), 0);
167 0x064, BIT(4), 0);
169 0x064, BIT(5), 0);
171 0x064, BIT(8), 0);
173 0x064, BIT(9), 0);
175 0x064, BIT(10), 0);
177 0x064, BIT(12), 0);
179 0x064, BIT(14), 0);
182 0x068, BIT(0), 0);
184 0x068, BIT(1), 0);
186 0x068, BIT(2), 0);
188 0x068, BIT(3), 0);
190 0x068, BIT(12), 0);
192 0x068, BIT(16), 0);
194 0x068, BIT(17), 0);
196 0x068, BIT(18), 0);
198 0x068, BIT(19), 0);
200 0x068, BIT(20), 0);
202 0x068, BIT(21), 0);
204 0x068, BIT(22), 0);
207 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
208 0, 4, /* M */
212 0);
215 0x088, 20, 3, 0);
217 0x088, 8, 3, 0);
219 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
220 0, 4, /* M */
224 0);
227 0x08c, 20, 3, 0);
229 0x08c, 8, 3, 0);
237 0x0b0, 16, 2, BIT(31), 0);
240 0x0b4, 16, 2, BIT(31), 0);
244 ir_parents, 0x0b8,
245 0, 4, /* M */
249 0);
252 0x0cc, BIT(1), 0);
255 0x100, BIT(0), 0);
257 0x100, BIT(1), 0);
259 "pll-ddr", 0x100, BIT(2), 0);
261 0x100, BIT(3), 0);
263 0x100, BIT(24), 0);
265 0x100, BIT(26), 0);
268 static const u8 de_table[] = { 0, 2, };
271 0x104, 0, 4, 24, 3, BIT(31), 0);
275 0x10c, 0, 4, 24, 3, BIT(31), 0);
278 static const u8 tcon_table[] = { 0, 2, };
281 0x118, 24, 3, BIT(31),
286 static const u8 deinterlace_table[] = { 0, 2, };
289 0x11c, 0, 4, 24, 3, BIT(31), 0);
293 static const u8 tve_clk2_table[] = { 0, 2, };
296 0x120, 0, 4, 24, 3, BIT(31), 0);
298 0x120, 8, 1, BIT(15), 0);
303 0x124, 0, 4, 24, 3, BIT(31), 0);
306 static const u8 csi_table[] = { 0, 5, };
308 0x120, 0, 4, 8, 3, BIT(15), 0);
314 static SUNXI_CCU_GATE(ve_clk, "ve", "pll-audio", 0x13c, BIT(31), 0);
316 static SUNXI_CCU_GATE(codec_clk, "codec", "pll-audio", 0x140, BIT(31), 0);
318 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x144, BIT(31), 0);
404 1, 2, 0);
481 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
483 [RST_BUS_DMA] = { 0x2c0, BIT(6) },
484 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
485 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
486 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
487 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
488 [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
489 [RST_BUS_OTG] = { 0x2c0, BIT(24) },
490 [RST_BUS_VE] = { 0x2c4, BIT(0) },
491 [RST_BUS_LCD] = { 0x2c4, BIT(4) },
492 [RST_BUS_DEINTERLACE] = { 0x2c4, BIT(5) },
493 [RST_BUS_CSI] = { 0x2c4, BIT(8) },
494 [RST_BUS_TVD] = { 0x2c4, BIT(9) },
495 [RST_BUS_TVE] = { 0x2c4, BIT(10) },
496 [RST_BUS_DE_BE] = { 0x2c4, BIT(12) },
497 [RST_BUS_DE_FE] = { 0x2c4, BIT(14) },
498 [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
499 [RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
500 [RST_BUS_IR] = { 0x2d0, BIT(2) },
501 [RST_BUS_RSB] = { 0x2d0, BIT(3) },
502 [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
503 [RST_BUS_I2C0] = { 0x2d0, BIT(16) },
504 [RST_BUS_I2C1] = { 0x2d0, BIT(17) },
505 [RST_BUS_I2C2] = { 0x2d0, BIT(18) },
506 [RST_BUS_UART0] = { 0x2d0, BIT(20) },
507 [RST_BUS_UART1] = { 0x2d0, BIT(21) },
508 [RST_BUS_UART2] = { 0x2d0, BIT(22) },
541 reg = devm_platform_ioremap_resource(pdev, 0); in suniv_f1c100s_ccu_probe()
561 return 0; in suniv_f1c100s_ccu_probe()