Lines Matching +full:csi +full:- +full:no +full:- +full:ss
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
6 #include <linux/clk-provider.h>
21 #include "ccu-sun9i-a80.h"
28 * Neither mainline Linux, U-boot, nor the vendor BSPs use these.
43 .hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M",
57 .hw.init = CLK_HW_INIT("pll-c1cpux", "osc24M",
79 .hw.init = CLK_HW_INIT("pll-audio", "osc24M",
84 /* Some PLLs are input * N / div1 / div2. Model them as NKMP with no K */
95 .hw.init = CLK_HW_INIT("pll-periph0", "osc24M",
111 .hw.init = CLK_HW_INIT("pll-ve", "osc24M",
127 .hw.init = CLK_HW_INIT("pll-ddr", "osc24M",
142 .hw.init = CLK_HW_INIT("pll-video0", "osc24M",
158 .hw.init = CLK_HW_INIT("pll-video1", "osc24M",
174 .hw.init = CLK_HW_INIT("pll-gpu", "osc24M",
190 .hw.init = CLK_HW_INIT("pll-de", "osc24M",
206 .hw.init = CLK_HW_INIT("pll-isp", "osc24M",
222 .hw.init = CLK_HW_INIT("pll-periph1", "osc24M",
228 static const char * const c0cpux_parents[] = { "osc24M", "pll-c0cpux" };
232 static const char * const c1cpux_parents[] = { "osc24M", "pll-c1cpux" };
258 static const char * const gtbus_parents[] = { "osc24M", "pll-periph0",
259 "pll-periph1", "pll-periph1" };
263 static const char * const ahb_parents[] = { "gtbus", "pll-periph0",
264 "pll-periph1", "pll-periph1" };
301 static const char * const apb_parents[] = { "osc24M", "pll-periph0" };
363 .hw.init = CLK_HW_INIT_PARENTS("out-a",
383 .hw.init = CLK_HW_INIT_PARENTS("out-b",
390 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0" };
392 static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_0_clk, "nand0-0", mod0_default_parents,
400 static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_1_clk, "nand0-1", mod0_default_parents,
408 static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_0_clk, "nand1-0", mod0_default_parents,
416 static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_1_clk, "nand1-1", mod0_default_parents,
432 static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0-sample", "mmc0",
434 static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0-output", "mmc0",
445 static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1-sample", "mmc1",
447 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1-output", "mmc1",
458 static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2-sample", "mmc2",
460 static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2-output", "mmc2",
471 static SUNXI_CCU_PHASE(mmc3_sample_clk, "mmc3-sample", "mmc3",
473 static SUNXI_CCU_PHASE(mmc3_output_clk, "mmc3-output", "mmc3",
484 static const char * const ss_parents[] = { "osc24M", "pll-periph",
485 "pll-periph1" };
494 .hw.init = CLK_HW_INIT_PARENTS("ss",
533 static SUNXI_CCU_M_WITH_GATE(i2s0_clk, "i2s0", "pll-audio",
535 static SUNXI_CCU_M_WITH_GATE(i2s1_clk, "i2s1", "pll-audio",
537 static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
540 static const char * const sdram_parents[] = { "pll-periph0", "pll-ddr" };
548 0, /* no gate */
551 static SUNXI_CCU_M_WITH_GATE(de_clk, "de", "pll-de", 0x490,
556 static const char * const mp_parents[] = { "pll-video1", "pll-gpu", "pll-de" };
565 static const char * const display_parents[] = { "pll-video0", "pll-video1" };
586 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(mipi_dsi0_clk, "mipi-dsi0",
594 static const char * const mipi_dsi1_parents[] = { "osc24M", "pll-video1" };
596 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(mipi_dsi1_clk, "mipi-dsi1",
613 static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 0x4b4, BIT(31), 0);
615 static SUNXI_CCU_M_WITH_GATE(mipi_csi_clk, "mipi-csi", "osc24M", 0x4bc,
618 static SUNXI_CCU_M_WITH_GATE(csi_isp_clk, "csi-isp", "pll-isp", 0x4c0,
621 static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", 0x4c0, BIT(16), 0);
623 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi0_mclk_clk, "csi0-mclk",
631 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi1_mclk_clk, "csi1-mclk",
639 static const char * const fd_parents[] = { "pll-periph0", "pll-isp" };
647 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 0x4d0,
652 static SUNXI_CCU_M_WITH_GATE(gpu_core_clk, "gpu-core", "pll-gpu", 0x4f0,
654 static SUNXI_CCU_M_WITH_GATE(gpu_memory_clk, "gpu-memory", "pll-gpu", 0x4f4,
657 static const char * const gpu_axi_parents[] = { "pll-periph0", "pll-gpu" };
659 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(gpu_axi_clk, "gpu-axi",
667 static SUNXI_CCU_M_WITH_GATE(sata_clk, "sata", "pll-periph0", 0x500,
670 static SUNXI_CCU_M_WITH_GATE(ac97_clk, "ac97", "pll-audio",
673 static SUNXI_CCU_M_WITH_MUX_GATE(mipi_hsi_clk, "mipi-hsi",
680 static const char * const gpadc_parents[] = { "osc24M", "pll-audio", "osc32k" };
705 .hw.init = CLK_HW_INIT_PARENTS("cir-tx",
713 static SUNXI_CCU_GATE(bus_fd_clk, "bus-fd", "ahb0",
715 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb0",
717 static SUNXI_CCU_GATE(bus_gpu_ctrl_clk, "bus-gpu-ctrl", "ahb0",
719 static SUNXI_CCU_GATE(bus_ss_clk, "bus-ss", "ahb0",
721 static SUNXI_CCU_GATE(bus_mmc_clk, "bus-mmc", "ahb0",
723 static SUNXI_CCU_GATE(bus_nand0_clk, "bus-nand0", "ahb0",
725 static SUNXI_CCU_GATE(bus_nand1_clk, "bus-nand1", "ahb0",
727 static SUNXI_CCU_GATE(bus_sdram_clk, "bus-sdram", "ahb0",
729 static SUNXI_CCU_GATE(bus_mipi_hsi_clk, "bus-mipi-hsi", "ahb0",
731 static SUNXI_CCU_GATE(bus_sata_clk, "bus-sata", "ahb0",
733 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb0",
735 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb0",
737 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb0",
739 static SUNXI_CCU_GATE(bus_spi2_clk, "bus-spi2", "ahb0",
741 static SUNXI_CCU_GATE(bus_spi3_clk, "bus-spi3", "ahb0",
745 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
747 static SUNXI_CCU_GATE(bus_usb_clk, "bus-usb", "ahb1",
749 static SUNXI_CCU_GATE(bus_gmac_clk, "bus-gmac", "ahb1",
751 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
753 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
755 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
757 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
761 static SUNXI_CCU_GATE(bus_lcd0_clk, "bus-lcd0", "ahb2",
763 static SUNXI_CCU_GATE(bus_lcd1_clk, "bus-lcd1", "ahb2",
765 static SUNXI_CCU_GATE(bus_edp_clk, "bus-edp", "ahb2",
767 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb2",
769 static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb2",
771 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb2",
773 static SUNXI_CCU_GATE(bus_mp_clk, "bus-mp", "ahb2",
775 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb2",
779 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb0",
781 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb0",
783 static SUNXI_CCU_GATE(bus_ac97_clk, "bus-ac97", "apb0",
785 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb0",
787 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb0",
789 static SUNXI_CCU_GATE(bus_lradc_clk, "bus-lradc", "apb0",
791 static SUNXI_CCU_GATE(bus_gpadc_clk, "bus-gpadc", "apb0",
793 static SUNXI_CCU_GATE(bus_twd_clk, "bus-twd", "apb0",
795 static SUNXI_CCU_GATE(bus_cir_tx_clk, "bus-cir-tx", "apb0",
799 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb1",
801 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb1",
803 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb1",
805 static SUNXI_CCU_GATE(bus_i2c3_clk, "bus-i2c3", "apb1",
807 static SUNXI_CCU_GATE(bus_i2c4_clk, "bus-i2c4", "apb1",
809 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb1",
811 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb1",
813 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb1",
815 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb1",
817 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb1",
819 static SUNXI_CCU_GATE(bus_uart5_clk, "bus-uart5", "apb1",
1204 val &= ~GENMASK(SUN9I_A80_PLL_N_SHIFT + SUN9I_A80_PLL_N_WIDTH - 1, in sun9i_a80_cpu_pll_fixup()
1232 return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun9i_a80_ccu_desc); in sun9i_a80_ccu_probe()
1236 { .compatible = "allwinner,sun9i-a80-ccu" },
1244 .name = "sun9i-a80-ccu",