Lines Matching full:ahb0
270 .hw.init = CLK_HW_INIT_PARENTS("ahb0",
712 /* AHB0 bus gates */
713 static SUNXI_CCU_GATE(bus_fd_clk, "bus-fd", "ahb0",
715 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb0",
717 static SUNXI_CCU_GATE(bus_gpu_ctrl_clk, "bus-gpu-ctrl", "ahb0",
719 static SUNXI_CCU_GATE(bus_ss_clk, "bus-ss", "ahb0",
721 static SUNXI_CCU_GATE(bus_mmc_clk, "bus-mmc", "ahb0",
723 static SUNXI_CCU_GATE(bus_nand0_clk, "bus-nand0", "ahb0",
725 static SUNXI_CCU_GATE(bus_nand1_clk, "bus-nand1", "ahb0",
727 static SUNXI_CCU_GATE(bus_sdram_clk, "bus-sdram", "ahb0",
729 static SUNXI_CCU_GATE(bus_mipi_hsi_clk, "bus-mipi-hsi", "ahb0",
731 static SUNXI_CCU_GATE(bus_sata_clk, "bus-sata", "ahb0",
733 static SUNXI_CCU_GATE(bus_ts_clk, "bus-ts", "ahb0",
735 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb0",
737 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb0",
739 static SUNXI_CCU_GATE(bus_spi2_clk, "bus-spi2", "ahb0",
741 static SUNXI_CCU_GATE(bus_spi3_clk, "bus-spi3", "ahb0",
907 /* AHB0 bus gates */
1112 /* AHB0 reset controls */