Lines Matching +full:0 +full:x584
23 #define CCU_SUN9I_LOCK_REG 0x09c
32 #define SUN9I_A80_PLL_C0CPUX_REG 0x000
33 #define SUN9I_A80_PLL_C1CPUX_REG 0x004
37 .lock = BIT(0),
38 .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
52 .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
66 * and 24.576 MHz, ignore them for now. Enforce d1 = 0 and d2 = 0.
68 #define SUN9I_A80_PLL_AUDIO_REG 0x008
73 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
74 .m = _SUNXI_CCU_DIV_OFFSET(0, 6, 0),
76 .reg = 0x008,
88 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
92 .reg = 0x00c,
104 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
108 .reg = 0x010,
120 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
124 .reg = 0x014,
136 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
139 .reg = 0x018,
151 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
153 .p = _SUNXI_CCU_DIV(0, 2), /* external divider p */
155 .reg = 0x01c,
167 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
171 .reg = 0x020,
183 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
187 .reg = 0x024,
199 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
203 .reg = 0x028,
215 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
219 .reg = 0x028,
230 0x50, 0, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
234 0x50, 8, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
237 { .val = 0, .div = 1 },
248 static SUNXI_CCU_M(atb0_clk, "atb0", "c0cpux", 0x054, 8, 2, 0);
251 0x054, 0, 3, axi_div_table, 0);
253 static SUNXI_CCU_M(atb1_clk, "atb1", "c1cpux", 0x058, 8, 2, 0);
256 0x058, 0, 3, axi_div_table, 0);
261 0x05c, 0, 2, 24, 2, CLK_IS_CRITICAL);
266 .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),
269 .reg = 0x060,
273 0),
278 .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),
281 .reg = 0x064,
285 0),
290 .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),
293 .reg = 0x068,
297 0),
304 .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),
307 .reg = 0x070,
311 0),
316 .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),
319 .reg = 0x074,
323 0),
328 .div = _SUNXI_CCU_DIV_FLAGS(0, 2, CLK_DIVIDER_POWER_OF_TWO),
331 .reg = 0x078,
340 0x080, 0, 3, 24, 2, BIT(31), 0);
343 0x084, 0, 3, 24, 2, BIT(31), 0);
347 .index = 0, .div = 750
361 .reg = 0x180,
366 0),
381 .reg = 0x184,
386 0),
392 static SUNXI_CCU_MP_WITH_MUX_GATE(nand0_0_clk, "nand0-0", mod0_default_parents,
393 0x400,
394 0, 4, /* M */
398 0);
401 0x404,
402 0, 4, /* M */
406 0);
408 static SUNXI_CCU_MP_WITH_MUX_GATE(nand1_0_clk, "nand1-0", mod0_default_parents,
409 0x408,
410 0, 4, /* M */
414 0);
417 0x40c,
418 0, 4, /* M */
422 0);
425 0x410,
426 0, 4, /* M */
430 0);
433 0x410, 20, 3, 0);
435 0x410, 8, 3, 0);
438 0x414,
439 0, 4, /* M */
443 0);
446 0x414, 20, 3, 0);
448 0x414, 8, 3, 0);
451 0x418,
452 0, 4, /* M */
456 0);
459 0x418, 20, 3, 0);
461 0x418, 8, 3, 0);
464 0x41c,
465 0, 4, /* M */
469 0);
472 0x41c, 20, 3, 0);
474 0x41c, 8, 3, 0);
477 0x428,
478 0, 4, /* M */
482 0);
486 static const u8 ss_table[] = { 0, 1, 13 };
489 .m = _SUNXI_CCU_DIV(0, 4),
493 .reg = 0x42c,
497 0),
502 0x430,
503 0, 4, /* M */
507 0);
510 0x434,
511 0, 4, /* M */
515 0);
518 0x438,
519 0, 4, /* M */
523 0);
526 0x43c,
527 0, 4, /* M */
531 0);
534 0x440, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
536 0x444, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
538 0x44c, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
541 static const u8 sdram_table[] = { 0, 3 };
545 0x484,
548 0, /* no gate */
551 static SUNXI_CCU_M_WITH_GATE(de_clk, "de", "pll-de", 0x490,
552 0, 4, BIT(31), CLK_SET_RATE_PARENT);
554 static SUNXI_CCU_GATE(edp_clk, "edp", "osc24M", 0x494, BIT(31), 0);
559 0x498,
560 0, 4, /* M */
563 0);
570 0x49c,
571 0, 4, /* M */
579 0x4a0,
580 0, 4, /* M */
588 0x4a8,
589 0, 4, /* M */
595 static const u8 mipi_dsi1_table[] = { 0, 9 };
598 0x4ac,
599 0, 4, /* M */
606 0x4b0,
607 0, 4, /* M */
613 static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 0x4b4, BIT(31), 0);
615 static SUNXI_CCU_M_WITH_GATE(mipi_csi_clk, "mipi-csi", "osc24M", 0x4bc,
616 0, 4, BIT(31), 0);
618 static SUNXI_CCU_M_WITH_GATE(csi_isp_clk, "csi-isp", "pll-isp", 0x4c0,
619 0, 4, BIT(31), CLK_SET_RATE_PARENT);
621 static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", 0x4c0, BIT(16), 0);
625 0x4c4,
626 0, 4, /* M */
633 0x4c8,
634 0, 4, /* M */
642 0x4cc,
643 0, 4, /* M */
646 0);
647 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 0x4d0,
650 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x4d4, BIT(31), 0);
652 static SUNXI_CCU_M_WITH_GATE(gpu_core_clk, "gpu-core", "pll-gpu", 0x4f0,
653 0, 3, BIT(31), CLK_SET_RATE_PARENT);
654 static SUNXI_CCU_M_WITH_GATE(gpu_memory_clk, "gpu-memory", "pll-gpu", 0x4f4,
655 0, 3, BIT(31), CLK_SET_RATE_PARENT);
661 0x4f8,
662 0, 4, /* M */
667 static SUNXI_CCU_M_WITH_GATE(sata_clk, "sata", "pll-periph0", 0x500,
668 0, 4, BIT(31), 0);
671 0x504, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
674 mod0_default_parents, 0x508,
675 0, 4, /* M */
678 0);
681 static const u8 gpadc_table[] = { 0, 4, 7 };
684 .m = _SUNXI_CCU_DIV(0, 4),
688 .reg = 0x50c,
692 0),
697 static const u8 cir_tx_table[] = { 0, 7 };
700 .m = _SUNXI_CCU_DIV(0, 4),
704 .reg = 0x510,
708 0),
714 0x580, BIT(0), 0);
716 0x580, BIT(1), 0);
718 0x580, BIT(3), 0);
720 0x580, BIT(5), 0);
722 0x580, BIT(8), 0);
724 0x580, BIT(12), 0);
726 0x580, BIT(13), 0);
728 0x580, BIT(14), 0);
730 0x580, BIT(15), 0);
732 0x580, BIT(16), 0);
734 0x580, BIT(18), 0);
736 0x580, BIT(20), 0);
738 0x580, BIT(21), 0);
740 0x580, BIT(22), 0);
742 0x580, BIT(23), 0);
746 0x584, BIT(0), 0);
748 0x584, BIT(1), 0);
750 0x584, BIT(17), 0);
752 0x584, BIT(21), 0);
754 0x584, BIT(22), 0);
756 0x584, BIT(23), 0);
758 0x584, BIT(24), 0);
762 0x588, BIT(0), 0);
764 0x588, BIT(1), 0);
766 0x588, BIT(2), 0);
768 0x588, BIT(4), 0);
770 0x588, BIT(5), 0);
772 0x588, BIT(7), 0);
774 0x588, BIT(8), 0);
776 0x588, BIT(11), 0);
780 0x590, BIT(1), 0);
782 0x590, BIT(5), 0);
784 0x590, BIT(11), 0);
786 0x590, BIT(12), 0);
788 0x590, BIT(13), 0);
790 0x590, BIT(15), 0);
792 0x590, BIT(17), 0);
794 0x590, BIT(18), 0);
796 0x590, BIT(19), 0);
800 0x594, BIT(0), 0);
802 0x594, BIT(1), 0);
804 0x594, BIT(2), 0);
806 0x594, BIT(3), 0);
808 0x594, BIT(4), 0);
810 0x594, BIT(16), 0);
812 0x594, BIT(17), 0);
814 0x594, BIT(18), 0);
816 0x594, BIT(19), 0);
818 0x594, BIT(20), 0);
820 0x594, BIT(21), 0);
1113 [RST_BUS_FD] = { 0x5a0, BIT(0) },
1114 [RST_BUS_VE] = { 0x5a0, BIT(1) },
1115 [RST_BUS_GPU_CTRL] = { 0x5a0, BIT(3) },
1116 [RST_BUS_SS] = { 0x5a0, BIT(5) },
1117 [RST_BUS_MMC] = { 0x5a0, BIT(8) },
1118 [RST_BUS_NAND0] = { 0x5a0, BIT(12) },
1119 [RST_BUS_NAND1] = { 0x5a0, BIT(13) },
1120 [RST_BUS_SDRAM] = { 0x5a0, BIT(14) },
1121 [RST_BUS_SATA] = { 0x5a0, BIT(16) },
1122 [RST_BUS_TS] = { 0x5a0, BIT(18) },
1123 [RST_BUS_SPI0] = { 0x5a0, BIT(20) },
1124 [RST_BUS_SPI1] = { 0x5a0, BIT(21) },
1125 [RST_BUS_SPI2] = { 0x5a0, BIT(22) },
1126 [RST_BUS_SPI3] = { 0x5a0, BIT(23) },
1129 [RST_BUS_OTG] = { 0x5a4, BIT(0) },
1130 [RST_BUS_OTG_PHY] = { 0x5a4, BIT(1) },
1131 [RST_BUS_MIPI_HSI] = { 0x5a4, BIT(9) },
1132 [RST_BUS_GMAC] = { 0x5a4, BIT(17) },
1133 [RST_BUS_MSGBOX] = { 0x5a4, BIT(21) },
1134 [RST_BUS_SPINLOCK] = { 0x5a4, BIT(22) },
1135 [RST_BUS_HSTIMER] = { 0x5a4, BIT(23) },
1136 [RST_BUS_DMA] = { 0x5a4, BIT(24) },
1139 [RST_BUS_LCD0] = { 0x5a8, BIT(0) },
1140 [RST_BUS_LCD1] = { 0x5a8, BIT(1) },
1141 [RST_BUS_EDP] = { 0x5a8, BIT(2) },
1142 [RST_BUS_LVDS] = { 0x5a8, BIT(3) },
1143 [RST_BUS_CSI] = { 0x5a8, BIT(4) },
1144 [RST_BUS_HDMI0] = { 0x5a8, BIT(5) },
1145 [RST_BUS_HDMI1] = { 0x5a8, BIT(6) },
1146 [RST_BUS_DE] = { 0x5a8, BIT(7) },
1147 [RST_BUS_MP] = { 0x5a8, BIT(8) },
1148 [RST_BUS_GPU] = { 0x5a8, BIT(9) },
1149 [RST_BUS_MIPI_DSI] = { 0x5a8, BIT(11) },
1152 [RST_BUS_SPDIF] = { 0x5b0, BIT(1) },
1153 [RST_BUS_AC97] = { 0x5b0, BIT(11) },
1154 [RST_BUS_I2S0] = { 0x5b0, BIT(12) },
1155 [RST_BUS_I2S1] = { 0x5b0, BIT(13) },
1156 [RST_BUS_LRADC] = { 0x5b0, BIT(15) },
1157 [RST_BUS_GPADC] = { 0x5b0, BIT(17) },
1158 [RST_BUS_CIR_TX] = { 0x5b0, BIT(19) },
1161 [RST_BUS_I2C0] = { 0x5b4, BIT(0) },
1162 [RST_BUS_I2C1] = { 0x5b4, BIT(1) },
1163 [RST_BUS_I2C2] = { 0x5b4, BIT(2) },
1164 [RST_BUS_I2C3] = { 0x5b4, BIT(3) },
1165 [RST_BUS_I2C4] = { 0x5b4, BIT(4) },
1166 [RST_BUS_UART0] = { 0x5b4, BIT(16) },
1167 [RST_BUS_UART1] = { 0x5b4, BIT(17) },
1168 [RST_BUS_UART2] = { 0x5b4, BIT(18) },
1169 [RST_BUS_UART3] = { 0x5b4, BIT(19) },
1170 [RST_BUS_UART4] = { 0x5b4, BIT(20) },
1171 [RST_BUS_UART5] = { 0x5b4, BIT(21) },
1219 reg = devm_platform_ioremap_resource(pdev, 0); in sun9i_a80_ccu_probe()
1223 /* Enforce d1 = 0, d2 = 0 for Audio PLL */ in sun9i_a80_ccu_probe()