Lines Matching +full:pll +full:- +full:periph
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2017 Chen-Yu Tsai. All rights reserved.
6 #include <linux/clk-provider.h>
22 #include "ccu-sun8i-a83t.h"
29 * Neither mainline Linux, U-boot, nor the vendor BSPs use these.
44 .hw.init = CLK_HW_INIT("pll-c0cpux", "osc24M",
58 .hw.init = CLK_HW_INIT("pll-c1cpux", "osc24M",
65 * The Audio PLL has d1, d2 dividers in addition to the usual N, M
66 * factors. Since we only need 2 frequencies from this PLL: 22.5792 MHz
92 .hw.init = CLK_HW_INIT("pll-audio", "osc24M",
109 .hw.init = CLK_HW_INIT("pll-video0", "osc24M",
125 .hw.init = CLK_HW_INIT("pll-ve", "osc24M",
141 .hw.init = CLK_HW_INIT("pll-ddr", "osc24M",
157 .hw.init = CLK_HW_INIT("pll-periph", "osc24M",
173 .hw.init = CLK_HW_INIT("pll-gpu", "osc24M",
189 .hw.init = CLK_HW_INIT("pll-hsic", "osc24M",
205 .hw.init = CLK_HW_INIT("pll-de", "osc24M",
222 .hw.init = CLK_HW_INIT("pll-video1", "osc24M",
228 static const char * const c0cpux_parents[] = { "osc24M", "pll-c0cpux" };
232 static const char * const c1cpux_parents[] = { "osc24M", "pll-c1cpux" };
239 static const char * const ahb1_parents[] = { "osc16M-d512", "osc24M",
240 "pll-periph",
241 "pll-periph" };
266 static const char * const apb2_parents[] = { "osc16M-d512", "osc24M",
267 "pll-periph", "pll-periph" };
275 static const char * const ahb2_parents[] = { "ahb1", "pll-periph" };
295 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
297 static SUNXI_CCU_GATE(bus_ss_clk, "bus-ss", "ahb1",
299 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
301 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
303 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
305 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
307 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
309 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
311 static SUNXI_CCU_GATE(bus_emac_clk, "bus-emac", "ahb2",
313 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
315 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
317 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
319 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
321 static SUNXI_CCU_GATE(bus_ehci0_clk, "bus-ehci0", "ahb2",
323 static SUNXI_CCU_GATE(bus_ehci1_clk, "bus-ehci1", "ahb2",
325 static SUNXI_CCU_GATE(bus_ohci0_clk, "bus-ohci0", "ahb2",
328 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
330 static SUNXI_CCU_GATE(bus_tcon0_clk, "bus-tcon0", "ahb1",
332 static SUNXI_CCU_GATE(bus_tcon1_clk, "bus-tcon1", "ahb1",
334 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
336 static SUNXI_CCU_GATE(bus_hdmi_clk, "bus-hdmi", "ahb1",
338 static SUNXI_CCU_GATE(bus_de_clk, "bus-de", "ahb1",
340 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
342 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
344 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
347 static SUNXI_CCU_GATE(bus_spdif_clk, "bus-spdif", "apb1",
349 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
351 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
353 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
355 static SUNXI_CCU_GATE(bus_i2s2_clk, "bus-i2s2", "apb1",
357 static SUNXI_CCU_GATE(bus_tdm_clk, "bus-tdm", "apb1",
360 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
362 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
364 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
366 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
368 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
370 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
372 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
374 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
377 static const char * const cci400_parents[] = { "osc24M", "pll-periph",
378 "pll-hsic" };
391 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
409 static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0-sample", "mmc0",
411 static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0-output", "mmc0",
422 static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1-sample", "mmc1",
424 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1-output", "mmc1",
430 static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2-sample", "mmc2",
432 static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2-output", "mmc2",
459 static SUNXI_CCU_M_WITH_GATE(i2s0_clk, "i2s0", "pll-audio",
461 static SUNXI_CCU_M_WITH_GATE(i2s1_clk, "i2s1", "pll-audio",
463 static SUNXI_CCU_M_WITH_GATE(i2s2_clk, "i2s2", "pll-audio",
465 static SUNXI_CCU_M_WITH_GATE(tdm_clk, "tdm", "pll-audio",
467 static SUNXI_CCU_M_WITH_GATE(spdif_clk, "spdif", "pll-audio",
470 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
472 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
474 static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic",
482 .hw.init = CLK_HW_INIT("usb-hsic-12m", "osc24M",
486 static SUNXI_CCU_GATE(usb_ohci0_clk, "usb-ohci0", "osc24M",
490 static SUNXI_CCU_M(dram_clk, "dram", "pll-ddr", 0x0f4, 0, 4, CLK_IS_CRITICAL);
492 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
494 static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram",
497 static const char * const tcon0_parents[] = { "pll-video0" };
501 static const char * const tcon1_parents[] = { "pll-video1" };
505 static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", 0x130, BIT(16), 0);
507 static SUNXI_CCU_GATE(mipi_csi_clk, "mipi-csi", "osc24M", 0x130, BIT(31), 0);
509 static const char * const csi_mclk_parents[] = { "pll-video0", "pll-de",
512 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_mclk_clk, "csi-mclk",
520 static const char * const csi_sclk_parents[] = { "pll-periph", "pll-ve" };
522 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_sclk_clk, "csi-sclk",
530 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 0x13c,
535 static const char * const hdmi_parents[] = { "pll-video1" };
543 static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 0x154, BIT(31), 0);
545 static const char * const mbus_parents[] = { "osc24M", "pll-periph",
546 "pll-ddr" };
554 static const char * const mipi_dsi0_parents[] = { "pll-video0" };
556 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(mipi_dsi0_clk, "mipi-dsi0",
564 static const char * const mipi_dsi1_parents[] = { "osc24M", "pll-video0" };
566 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(mipi_dsi1_clk, "mipi-dsi1",
574 static SUNXI_CCU_M_WITH_GATE(gpu_core_clk, "gpu-core", "pll-gpu", 0x1a0,
577 static const char * const gpu_memory_parents[] = { "pll-gpu", "pll-ddr" };
578 static SUNXI_CCU_M_WITH_MUX_GATE(gpu_memory_clk, "gpu-memory",
586 static SUNXI_CCU_M_WITH_GATE(gpu_hyd_clk, "gpu-hyd", "pll-gpu", 0x1a8,
878 val &= ~GENMASK(SUN8I_A83T_PLL_N_SHIFT + SUN8I_A83T_PLL_N_WIDTH - 1, in sun8i_a83t_cpu_pll_fixup()
897 /* Enforce d1 = 0, d2 = 1 for Audio PLL */ in sun8i_a83t_ccu_probe()
907 return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun8i_a83t_ccu_desc); in sun8i_a83t_ccu_probe()
911 { .compatible = "allwinner,sun8i-a83t-ccu" },
919 .name = "sun8i-a83t-ccu",