Lines Matching +full:0 +full:x2d0
24 #define CCU_SUN8I_A83T_LOCK_REG 0x20c
33 #define SUN8I_A83T_PLL_C0CPUX_REG 0x000
34 #define SUN8I_A83T_PLL_C1CPUX_REG 0x004
38 .lock = BIT(0),
39 .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
53 .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
68 * which is d1 = 0, d2 = 1.
70 #define SUN8I_A83T_PLL_AUDIO_REG 0x008
74 { .rate = 45158400, .pattern = 0xc00121ff, .m = 29, .n = 54 },
75 { .rate = 49152000, .pattern = 0xc000e147, .m = 30, .n = 61 },
81 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
82 .m = _SUNXI_CCU_DIV(0, 6),
85 0x284, BIT(31)),
101 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
103 .p = _SUNXI_CCU_DIV(0, 2), /* output divider */
106 .reg = 0x010,
118 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
122 .reg = 0x018,
138 .reg = 0x020,
150 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
154 .reg = 0x028,
166 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
170 .reg = 0x038,
182 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
186 .reg = 0x044,
198 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
202 .reg = 0x048,
214 .n = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 8, 0, 12, 0),
216 .p = _SUNXI_CCU_DIV(0, 2), /* external divider p */
219 .reg = 0x04c,
230 0x50, 12, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
234 0x50, 28, 1, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
236 static SUNXI_CCU_M(axi0_clk, "axi0", "c0cpux", 0x050, 0, 2, 0);
237 static SUNXI_CCU_M(axi1_clk, "axi1", "c1cpux", 0x050, 16, 2, 0);
256 .reg = 0x054,
260 0),
264 static SUNXI_CCU_M(apb1_clk, "apb1", "ahb1", 0x054, 8, 2, 0);
269 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
270 0, 5, /* M */
273 0);
281 .shift = 0,
287 .reg = 0x05c,
291 0),
296 0x060, BIT(1), 0);
298 0x060, BIT(5), 0);
300 0x060, BIT(6), 0);
302 0x060, BIT(8), 0);
304 0x060, BIT(9), 0);
306 0x060, BIT(10), 0);
308 0x060, BIT(13), 0);
310 0x060, BIT(14), 0);
312 0x060, BIT(17), 0);
314 0x060, BIT(19), 0);
316 0x060, BIT(20), 0);
318 0x060, BIT(21), 0);
320 0x060, BIT(24), 0);
322 0x060, BIT(26), 0);
324 0x060, BIT(27), 0);
326 0x060, BIT(29), 0);
329 0x064, BIT(0), 0);
331 0x064, BIT(4), 0);
333 0x064, BIT(5), 0);
335 0x064, BIT(8), 0);
337 0x064, BIT(11), 0);
339 0x064, BIT(12), 0);
341 0x064, BIT(20), 0);
343 0x064, BIT(21), 0);
345 0x064, BIT(22), 0);
348 0x068, BIT(1), 0);
350 0x068, BIT(5), 0);
352 0x068, BIT(12), 0);
354 0x068, BIT(13), 0);
356 0x068, BIT(14), 0);
358 0x068, BIT(15), 0);
361 0x06c, BIT(0), 0);
363 0x06c, BIT(1), 0);
365 0x06c, BIT(2), 0);
367 0x06c, BIT(16), 0);
369 0x06c, BIT(17), 0);
371 0x06c, BIT(18), 0);
373 0x06c, BIT(19), 0);
375 0x06c, BIT(20), 0);
380 .div = _SUNXI_CCU_DIV_FLAGS(0, 2, 0),
383 .reg = 0x078,
394 0x080,
395 0, 4, /* M */
399 0);
402 0x088,
403 0, 4, /* M */
407 0);
410 0x088, 20, 3, 0);
412 0x088, 8, 3, 0);
415 0x08c,
416 0, 4, /* M */
420 0);
423 0x08c, 20, 3, 0);
425 0x08c, 8, 3, 0);
428 0x090, 0);
431 0x090, 20, 3, 0);
433 0x090, 8, 3, 0);
436 0x09c,
437 0, 4, /* M */
441 0);
444 0x0a0,
445 0, 4, /* M */
449 0);
452 0x0a4,
453 0, 4, /* M */
457 0);
460 0x0b0, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
462 0x0b4, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
464 0x0b8, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
466 0x0bc, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
468 0x0c0, 0, 4, BIT(31), CLK_SET_RATE_PARENT);
471 0x0cc, BIT(8), 0);
473 0x0cc, BIT(9), 0);
475 0x0cc, BIT(10), 0);
479 .reg = 0x0cc,
483 &ccu_gate_ops, 0),
487 0x0cc, BIT(16), 0);
490 static SUNXI_CCU_M(dram_clk, "dram", "pll-ddr", 0x0f4, 0, 4, CLK_IS_CRITICAL);
493 0x100, BIT(0), 0);
495 0x100, BIT(1), 0);
499 0x118, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
503 0x11c, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
505 static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", 0x130, BIT(16), 0);
507 static SUNXI_CCU_GATE(mipi_csi_clk, "mipi-csi", "osc24M", 0x130, BIT(31), 0);
511 static const u8 csi_mclk_table[] = { 0, 3, 5 };
514 0x134,
515 0, 5, /* M */
518 0);
521 static const u8 csi_sclk_table[] = { 0, 5 };
524 0x134,
528 0);
530 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve", 0x13c,
533 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M", 0x144, BIT(31), 0);
537 0x150,
538 0, 4, /* M */
543 static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M", 0x154, BIT(31), 0);
548 0x15c,
549 0, 3, /* M */
558 0x168,
559 0, 4, /* M */
565 static const u8 mipi_dsi1_table[] = { 0, 9 };
568 0x16c,
569 0, 4, /* M */
574 static SUNXI_CCU_M_WITH_GATE(gpu_core_clk, "gpu-core", "pll-gpu", 0x1a0,
575 0, 3, BIT(31), CLK_SET_RATE_PARENT);
580 0x1a4,
581 0, 3, /* M */
586 static SUNXI_CCU_M_WITH_GATE(gpu_hyd_clk, "gpu-hyd", "pll-gpu", 0x1a8,
587 0, 3, BIT(31), CLK_SET_RATE_PARENT);
801 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
802 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
803 [RST_USB_HSIC] = { 0x0cc, BIT(2) },
804 [RST_DRAM] = { 0x0f4, BIT(31) },
805 [RST_MBUS] = { 0x0fc, BIT(31) },
806 [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
807 [RST_BUS_SS] = { 0x2c0, BIT(5) },
808 [RST_BUS_DMA] = { 0x2c0, BIT(6) },
809 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
810 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
811 [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
812 [RST_BUS_NAND] = { 0x2c0, BIT(13) },
813 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
814 [RST_BUS_EMAC] = { 0x2c0, BIT(17) },
815 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
816 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
817 [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
818 [RST_BUS_OTG] = { 0x2c0, BIT(24) },
819 [RST_BUS_EHCI0] = { 0x2c0, BIT(26) },
820 [RST_BUS_EHCI1] = { 0x2c0, BIT(27) },
821 [RST_BUS_OHCI0] = { 0x2c0, BIT(29) },
822 [RST_BUS_VE] = { 0x2c4, BIT(0) },
823 [RST_BUS_TCON0] = { 0x2c4, BIT(4) },
824 [RST_BUS_TCON1] = { 0x2c4, BIT(5) },
825 [RST_BUS_CSI] = { 0x2c4, BIT(8) },
826 [RST_BUS_HDMI0] = { 0x2c4, BIT(10) },
827 [RST_BUS_HDMI1] = { 0x2c4, BIT(11) },
828 [RST_BUS_DE] = { 0x2c4, BIT(12) },
829 [RST_BUS_GPU] = { 0x2c4, BIT(20) },
830 [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
831 [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
832 [RST_BUS_LVDS] = { 0x2c8, BIT(0) },
833 [RST_BUS_SPDIF] = { 0x2d0, BIT(1) },
834 [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
835 [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
836 [RST_BUS_I2S2] = { 0x2d0, BIT(14) },
837 [RST_BUS_TDM] = { 0x2d0, BIT(15) },
838 [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
839 [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
840 [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
841 [RST_BUS_UART0] = { 0x2d8, BIT(16) },
842 [RST_BUS_UART1] = { 0x2d8, BIT(17) },
843 [RST_BUS_UART2] = { 0x2d8, BIT(18) },
844 [RST_BUS_UART3] = { 0x2d8, BIT(19) },
845 [RST_BUS_UART4] = { 0x2d8, BIT(20) },
893 reg = devm_platform_ioremap_resource(pdev, 0); in sun8i_a83t_ccu_probe()
897 /* Enforce d1 = 0, d2 = 1 for Audio PLL */ in sun8i_a83t_ccu_probe()