Lines Matching +full:24 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
25 #include "ccu-sun8i-a23-a33.h"
29 .enable = BIT(31),
30 .lock = BIT(28),
39 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
50 * With sigma-delta modulation for fractional-N on the audio PLL,
64 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
68 pll_audio_sdm_table, BIT(24),
69 0x284, BIT(31),
70 BIT(31), /* gate */
71 BIT(28), /* lock */
74 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
78 BIT(24), /* frac enable */
79 BIT(25), /* frac select */
82 BIT(31), /* gate */
83 BIT(28), /* lock */
86 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
90 BIT(24), /* frac enable */
91 BIT(25), /* frac select */
94 BIT(31), /* gate */
95 BIT(28), /* lock */
98 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
103 BIT(31), /* gate */
104 BIT(28), /* lock */
107 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph",
111 BIT(31), /* gate */
112 BIT(28), /* lock */
113 2, /* post-div */
116 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
120 BIT(24), /* frac enable */
121 BIT(25), /* frac select */
124 BIT(31), /* gate */
125 BIT(28), /* lock */
131 * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
136 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi",
137 "pll-video", 0x040,
141 BIT(31) | BIT(23) | BIT(22), /* gate */
142 BIT(28), /* lock */
145 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
149 BIT(24), /* frac enable */
150 BIT(25), /* frac select */
153 BIT(31), /* gate */
154 BIT(28), /* lock */
157 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
161 BIT(24), /* frac enable */
162 BIT(25), /* frac select */
165 BIT(31), /* gate */
166 BIT(28), /* lock */
170 "pll-cpux" , "pll-cpux" };
177 "axi" , "pll-periph" };
213 "pll-periph" , "pll-periph" };
217 24, 2, /* mux */
220 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
221 0x060, BIT(1), 0);
222 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
223 0x060, BIT(6), 0);
224 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
225 0x060, BIT(8), 0);
226 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
227 0x060, BIT(9), 0);
228 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
229 0x060, BIT(10), 0);
230 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
231 0x060, BIT(13), 0);
232 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
233 0x060, BIT(14), 0);
234 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
235 0x060, BIT(19), 0);
236 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
237 0x060, BIT(20), 0);
238 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
239 0x060, BIT(21), 0);
240 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
241 0x060, BIT(24), 0);
242 static SUNXI_CCU_GATE(bus_ehci_clk, "bus-ehci", "ahb1",
243 0x060, BIT(26), 0);
244 static SUNXI_CCU_GATE(bus_ohci_clk, "bus-ohci", "ahb1",
245 0x060, BIT(29), 0);
247 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
248 0x064, BIT(0), 0);
249 static SUNXI_CCU_GATE(bus_lcd_clk, "bus-lcd", "ahb1",
250 0x064, BIT(4), 0);
251 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
252 0x064, BIT(8), 0);
253 static SUNXI_CCU_GATE(bus_de_be_clk, "bus-de-be", "ahb1",
254 0x064, BIT(12), 0);
255 static SUNXI_CCU_GATE(bus_de_fe_clk, "bus-de-fe", "ahb1",
256 0x064, BIT(14), 0);
257 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
258 0x064, BIT(20), 0);
259 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
260 0x064, BIT(21), 0);
261 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
262 0x064, BIT(22), 0);
263 static SUNXI_CCU_GATE(bus_drc_clk, "bus-drc", "ahb1",
264 0x064, BIT(25), 0);
266 static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
267 0x068, BIT(0), 0);
268 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
269 0x068, BIT(5), 0);
270 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
271 0x068, BIT(12), 0);
272 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
273 0x068, BIT(13), 0);
275 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
276 0x06c, BIT(0), 0);
277 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
278 0x06c, BIT(1), 0);
279 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
280 0x06c, BIT(2), 0);
281 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
282 0x06c, BIT(16), 0);
283 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
284 0x06c, BIT(17), 0);
285 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
286 0x06c, BIT(18), 0);
287 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
288 0x06c, BIT(19), 0);
289 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
290 0x06c, BIT(20), 0);
292 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
296 24, 2, /* mux */
297 BIT(31), /* gate */
303 24, 2, /* mux */
304 BIT(31), /* gate */
315 24, 2, /* mux */
316 BIT(31), /* gate */
327 24, 2, /* mux */
328 BIT(31), /* gate */
339 24, 2, /* mux */
340 BIT(31), /* gate */
346 24, 2, /* mux */
347 BIT(31), /* gate */
350 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
351 "pll-audio-2x", "pll-audio" };
353 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
356 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
359 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
360 0x0cc, BIT(8), 0);
361 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
362 0x0cc, BIT(9), 0);
363 static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic",
364 0x0cc, BIT(10), 0);
365 static SUNXI_CCU_GATE(usb_hsic_12M_clk, "usb-hsic-12M", "osc24M",
366 0x0cc, BIT(11), 0);
367 static SUNXI_CCU_GATE(usb_ohci_clk, "usb-ohci", "osc24M",
368 0x0cc, BIT(16), 0);
370 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "pll-ddr",
371 0x100, BIT(0), 0);
372 static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "pll-ddr",
373 0x100, BIT(1), 0);
374 static SUNXI_CCU_GATE(dram_drc_clk, "dram-drc", "pll-ddr",
375 0x100, BIT(16), 0);
376 static SUNXI_CCU_GATE(dram_de_fe_clk, "dram-de-fe", "pll-ddr",
377 0x100, BIT(24), 0);
378 static SUNXI_CCU_GATE(dram_de_be_clk, "dram-de-be", "pll-ddr",
379 0x100, BIT(26), 0);
381 static const char * const de_parents[] = { "pll-video", "pll-periph-2x",
382 "pll-gpu", "pll-de" };
384 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_be_clk, "de-be",
386 0x104, 0, 4, 24, 3, BIT(31), 0);
388 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_fe_clk, "de-fe",
390 0x10c, 0, 4, 24, 3, BIT(31), 0);
392 static const char * const lcd_ch0_parents[] = { "pll-video", "pll-video-2x",
393 "pll-mipi" };
395 static SUNXI_CCU_MUX_TABLE_WITH_GATE(lcd_ch0_clk, "lcd-ch0",
397 0x118, 24, 3, BIT(31),
400 static const char * const lcd_ch1_parents[] = { "pll-video", "pll-video-2x" };
402 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(lcd_ch1_clk, "lcd-ch1",
404 0x12c, 0, 4, 24, 2, BIT(31), 0);
406 static const char * const csi_sclk_parents[] = { "pll-video", "pll-de",
407 "pll-mipi", "pll-ve" };
409 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_sclk_clk, "csi-sclk",
411 0x134, 16, 4, 24, 3, BIT(31), 0);
413 static const char * const csi_mclk_parents[] = { "pll-video", "pll-de",
416 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_mclk_clk, "csi-mclk",
418 0x134, 0, 5, 8, 3, BIT(15), 0);
420 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
421 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
423 static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
424 0x140, BIT(31), CLK_SET_RATE_PARENT);
426 0x144, BIT(31), 0);
428 static const char * const mbus_parents[] = { "osc24M", "pll-periph-2x",
429 "pll-ddr" };
431 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
433 static const char * const dsi_sclk_parents[] = { "pll-video", "pll-video-2x" };
435 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_sclk_clk, "dsi-sclk",
437 0x168, 16, 4, 24, 2, BIT(31), 0);
439 static const char * const dsi_dphy_parents[] = { "pll-video", "pll-periph" };
441 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
443 0x168, 0, 4, 8, 2, BIT(15), 0);
447 0x180, 0, 4, 24, 3, BIT(31), 0);
449 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
450 0x1a0, 0, 3, BIT(31), 0);
452 static const char * const ats_parents[] = { "osc24M", "pll-periph" };
454 0x1b0, 0, 3, 24, 2, BIT(31), 0);
552 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
555 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
558 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
561 static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
564 static CLK_FIXED_FACTOR_HW(pll_periph_2x_clk, "pll-periph-2x",
567 static CLK_FIXED_FACTOR_HW(pll_video_2x_clk, "pll-video-2x",
672 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
673 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
674 [RST_USB_HSIC] = { 0x0cc, BIT(2) },
676 [RST_MBUS] = { 0x0fc, BIT(31) },
678 [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
679 [RST_BUS_DMA] = { 0x2c0, BIT(6) },
680 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
681 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
682 [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
683 [RST_BUS_NAND] = { 0x2c0, BIT(13) },
684 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
685 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
686 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
687 [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
688 [RST_BUS_OTG] = { 0x2c0, BIT(24) },
689 [RST_BUS_EHCI] = { 0x2c0, BIT(26) },
690 [RST_BUS_OHCI] = { 0x2c0, BIT(29) },
692 [RST_BUS_VE] = { 0x2c4, BIT(0) },
693 [RST_BUS_LCD] = { 0x2c4, BIT(4) },
694 [RST_BUS_CSI] = { 0x2c4, BIT(8) },
695 [RST_BUS_DE_BE] = { 0x2c4, BIT(12) },
696 [RST_BUS_DE_FE] = { 0x2c4, BIT(14) },
697 [RST_BUS_GPU] = { 0x2c4, BIT(20) },
698 [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
699 [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
700 [RST_BUS_DRC] = { 0x2c4, BIT(25) },
702 [RST_BUS_LVDS] = { 0x2c8, BIT(0) },
704 [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
705 [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
706 [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
708 [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
709 [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
710 [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
711 [RST_BUS_UART0] = { 0x2d8, BIT(16) },
712 [RST_BUS_UART1] = { 0x2d8, BIT(17) },
713 [RST_BUS_UART2] = { 0x2d8, BIT(18) },
714 [RST_BUS_UART3] = { 0x2d8, BIT(19) },
715 [RST_BUS_UART4] = { 0x2d8, BIT(20) },
737 /* Force the PLL-Audio-1x divider to 1 */ in sun8i_a23_ccu_probe()
742 /* Force PLL-MIPI to MIPI mode */ in sun8i_a23_ccu_probe()
744 val &= ~BIT(16); in sun8i_a23_ccu_probe()
747 return devm_sunxi_ccu_probe(&pdev->dev, reg, &sun8i_a23_ccu_desc); in sun8i_a23_ccu_probe()
751 { .compatible = "allwinner,sun8i-a23-ccu" },
759 .name = "sun8i-a23-ccu",