Lines Matching +full:24 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2023-2024 Arm Ltd.
9 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/sun55i-a523-ccu.h>
15 #include <dt-bindings/reset/sun55i-a523-ccu.h>
32 * The 24 MHz oscillator, the root of most of the clock tree.
33 * .fw_name is the string used in the DT "clock-names" property, used to
47 .enable = BIT(27),
48 .lock = BIT(28),
54 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-ddr0", osc24M,
68 .enable = BIT(27),
69 .lock = BIT(28),
74 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-periph0-4x",
80 * Most clock-defining macros expect an *array* of parent clocks, even if
83 * a single-entry array out of that. The macros using _HWS take such an
93 static SUNXI_CCU_M_HWS(pll_periph0_2x_clk, "pll-periph0-2x",
98 static SUNXI_CCU_M_HWS(pll_periph0_800M_clk, "pll-periph0-800M",
100 static SUNXI_CCU_M_HWS(pll_periph0_480M_clk, "pll-periph0-480M",
105 static CLK_FIXED_FACTOR_HWS(pll_periph0_600M_clk, "pll-periph0-600M",
107 static CLK_FIXED_FACTOR_HWS(pll_periph0_400M_clk, "pll-periph0-400M",
109 static CLK_FIXED_FACTOR_HWS(pll_periph0_300M_clk, "pll-periph0-300M",
111 static CLK_FIXED_FACTOR_HWS(pll_periph0_200M_clk, "pll-periph0-200M",
113 static CLK_FIXED_FACTOR_HWS(pll_periph0_150M_clk, "pll-periph0-150M",
115 static CLK_FIXED_FACTOR_HWS(pll_periph0_160M_clk, "pll-periph0-160M",
123 .enable = BIT(27),
124 .lock = BIT(28),
129 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-periph1-4x",
138 static SUNXI_CCU_M_HWS(pll_periph1_2x_clk, "pll-periph1-2x",
140 static SUNXI_CCU_M_HWS(pll_periph1_800M_clk, "pll-periph1-800M",
142 static SUNXI_CCU_M_HWS(pll_periph1_480M_clk, "pll-periph1-480M",
148 static CLK_FIXED_FACTOR_HWS(pll_periph1_600M_clk, "pll-periph1-600M",
150 static CLK_FIXED_FACTOR_HWS(pll_periph1_400M_clk, "pll-periph1-400M",
152 static CLK_FIXED_FACTOR_HWS(pll_periph1_300M_clk, "pll-periph1-300M",
154 static CLK_FIXED_FACTOR_HWS(pll_periph1_200M_clk, "pll-periph1-200M",
156 static CLK_FIXED_FACTOR_HWS(pll_periph1_150M_clk, "pll-periph1-150M",
161 static CLK_FIXED_FACTOR_HWS(pll_periph1_160M_clk, "pll-periph1-160M",
166 .enable = BIT(27),
167 .lock = BIT(28),
173 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-gpu", osc24M,
181 .enable = BIT(27),
182 .lock = BIT(28),
187 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-video0-8x",
196 static SUNXI_CCU_M_HWS(pll_video0_4x_clk, "pll-video0-4x",
198 static CLK_FIXED_FACTOR_HWS(pll_video0_3x_clk, "pll-video0-3x",
203 .enable = BIT(27),
204 .lock = BIT(28),
209 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-video1-8x",
218 static SUNXI_CCU_M_HWS(pll_video1_4x_clk, "pll-video1-4x",
220 static CLK_FIXED_FACTOR_HWS(pll_video1_3x_clk, "pll-video1-3x",
225 .enable = BIT(27),
226 .lock = BIT(28),
231 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-video2-8x",
240 static SUNXI_CCU_M_HWS(pll_video2_4x_clk, "pll-video2-4x",
242 static CLK_FIXED_FACTOR_HWS(pll_video2_3x_clk, "pll-video2-3x",
247 .enable = BIT(27),
248 .lock = BIT(28),
254 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-ve", osc24M,
262 .enable = BIT(27),
263 .lock = BIT(28),
268 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-video3-8x",
277 static SUNXI_CCU_M_HWS(pll_video3_4x_clk, "pll-video3-4x",
279 static CLK_FIXED_FACTOR_HWS(pll_video3_3x_clk, "pll-video3-3x",
297 .enable = BIT(27),
298 .lock = BIT(28),
301 .sdm = _SUNXI_CCU_SDM(pll_audio0_sdm_table, BIT(24),
302 0x178, BIT(31)),
308 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-audio0-4x",
314 static CLK_FIXED_FACTOR_HW(pll_audio0_2x_clk, "pll-audio0-2x",
316 static CLK_FIXED_FACTOR_HW(pll_audio0_clk, "pll-audio0",
321 .enable = BIT(27),
322 .lock = BIT(28),
327 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-npu-4x",
332 static CLK_FIXED_FACTOR_HW(pll_npu_2x_clk, "pll-npu-2x",
335 static CLK_FIXED_FACTOR_HW(pll_npu_1x_clk, "pll-npu-1x",
352 24, 2, /* mux */
358 24, 2, /* mux */
371 24, 3, /* mux */
387 24, 3, /* mux */
388 BIT(31), /* gate */
407 24, 3, /* mux */
408 BIT(31), /* gate */
411 static SUNXI_CCU_GATE_HWS(bus_de_clk, "bus-de", ahb_hws, 0x60c, BIT(0), 0);
422 24, 3, /* mux */
423 BIT(31), /* gate */
426 static SUNXI_CCU_GATE_HWS(bus_di_clk, "bus-di", ahb_hws, 0x62c, BIT(0), 0);
437 24, 3, /* mux */
438 BIT(31), /* gate */
441 static SUNXI_CCU_GATE_HWS(bus_g2d_clk, "bus-g2d", ahb_hws, 0x63c, BIT(0), 0);
454 24, 3, /* mux */
455 BIT(31), /* gate */
458 static SUNXI_CCU_GATE_HWS(bus_gpu_clk, "bus-gpu", ahb_hws, 0x67c, BIT(0), 0);
468 24, 3, /* mux */
469 BIT(31), /* gate */
472 static SUNXI_CCU_GATE_HWS(bus_ce_clk, "bus-ce", ahb_hws, 0x68c, BIT(0), 0);
473 static SUNXI_CCU_GATE_HWS(bus_ce_sys_clk, "bus-ce-sys", ahb_hws, 0x68c,
474 BIT(1), 0);
484 24, 3, /* mux */
485 BIT(31), /* gate */
488 static SUNXI_CCU_GATE_HWS(bus_ve_clk, "bus-ve", ahb_hws, 0x69c, BIT(0), 0);
498 24, 3, /* mux */
499 BIT(31), /* gate */
502 static SUNXI_CCU_GATE_HWS(bus_dma_clk, "bus-dma", ahb_hws, 0x70c, BIT(0), 0);
504 static SUNXI_CCU_GATE_HWS(bus_msgbox_clk, "bus-msgbox", ahb_hws, 0x71c,
505 BIT(0), 0);
507 static SUNXI_CCU_GATE_HWS(bus_spinlock_clk, "bus-spinlock", ahb_hws, 0x72c,
508 BIT(0), 0);
520 24, 3, /* mux */
521 BIT(31), /* gate */
529 24, 3, /* mux */
530 BIT(31), /* gate */
538 24, 3, /* mux */
539 BIT(31), /* gate */
547 24, 3, /* mux */
548 BIT(31), /* gate */
556 24, 3, /* mux */
557 BIT(31), /* gate */
565 24, 3, /* mux */
566 BIT(31), /* gate */
569 static SUNXI_CCU_GATE_HWS(bus_hstimer_clk, "bus-hstimer", ahb_hws, 0x74c,
570 BIT(0), 0);
572 static SUNXI_CCU_GATE_HWS(bus_dbg_clk, "bus-dbg", ahb_hws, 0x78c,
573 BIT(0), 0);
575 static SUNXI_CCU_GATE_HWS(bus_pwm0_clk, "bus-pwm0", apb1_hws, 0x7ac, BIT(0), 0);
576 static SUNXI_CCU_GATE_HWS(bus_pwm1_clk, "bus-pwm1", apb1_hws, 0x7ac, BIT(1), 0);
591 24, 3, /* mux */
592 BIT(31), /* gate */
596 static SUNXI_CCU_GATE_HWS(bus_iommu_clk, "bus-iommu", apb0_hws, 0x7bc,
597 BIT(0), 0);
610 24, 3, /* mux */
611 BIT(31), /* gate */
615 static SUNXI_CCU_GATE_HWS(mbus_dma_clk, "mbus-dma", mbus_hws,
616 0x804, BIT(0), 0);
617 static SUNXI_CCU_GATE_HWS(mbus_ve_clk, "mbus-ve", mbus_hws,
618 0x804, BIT(1), 0);
619 static SUNXI_CCU_GATE_HWS(mbus_ce_clk, "mbus-ce", mbus_hws,
620 0x804, BIT(2), 0);
621 static SUNXI_CCU_GATE_HWS(mbus_nand_clk, "mbus-nand", mbus_hws,
622 0x804, BIT(5), 0);
623 static SUNXI_CCU_GATE_HWS(mbus_usb3_clk, "mbus-usb3", mbus_hws,
624 0x804, BIT(6), 0);
625 static SUNXI_CCU_GATE_HWS(mbus_csi_clk, "mbus-csi", mbus_hws,
626 0x804, BIT(8), 0);
627 static SUNXI_CCU_GATE_HWS(mbus_isp_clk, "mbus-isp", mbus_hws,
628 0x804, BIT(9), 0);
629 static SUNXI_CCU_GATE_HWS(mbus_gmac1_clk, "mbus-gmac1", mbus_hws,
630 0x804, BIT(12), 0);
632 static SUNXI_CCU_GATE_HWS(bus_dram_clk, "bus-dram", ahb_hws, 0x80c,
633 BIT(0), CLK_IS_CRITICAL);
646 24, 3, /* mux */
647 BIT(31), /* gate */
653 24, 3, /* mux */
654 BIT(31), /* gate */
657 static SUNXI_CCU_GATE_HWS(bus_nand_clk, "bus-nand", ahb_hws, 0x82c,
658 BIT(0), 0);
664 24, 3, /* mux */
665 BIT(31), /* gate */
673 24, 3, /* mux */
674 BIT(31), /* gate */
690 24, 3, /* mux */
691 BIT(31), /* gate */
695 static SUNXI_CCU_GATE_HWS(bus_mmc0_clk, "bus-mmc0", ahb_hws, 0x84c, BIT(0), 0);
696 static SUNXI_CCU_GATE_HWS(bus_mmc1_clk, "bus-mmc1", ahb_hws, 0x84c, BIT(1), 0);
697 static SUNXI_CCU_GATE_HWS(bus_mmc2_clk, "bus-mmc2", ahb_hws, 0x84c, BIT(2), 0);
699 static SUNXI_CCU_GATE_HWS(bus_sysdap_clk, "bus-sysdap", apb1_hws, 0x88c,
700 BIT(0), 0);
702 static SUNXI_CCU_GATE_HWS(bus_uart0_clk, "bus-uart0", apb1_hws, 0x90c,
703 BIT(0), 0);
704 static SUNXI_CCU_GATE_HWS(bus_uart1_clk, "bus-uart1", apb1_hws, 0x90c,
705 BIT(1), 0);
706 static SUNXI_CCU_GATE_HWS(bus_uart2_clk, "bus-uart2", apb1_hws, 0x90c,
707 BIT(2), 0);
708 static SUNXI_CCU_GATE_HWS(bus_uart3_clk, "bus-uart3", apb1_hws, 0x90c,
709 BIT(3), 0);
710 static SUNXI_CCU_GATE_HWS(bus_uart4_clk, "bus-uart4", apb1_hws, 0x90c,
711 BIT(4), 0);
712 static SUNXI_CCU_GATE_HWS(bus_uart5_clk, "bus-uart5", apb1_hws, 0x90c,
713 BIT(5), 0);
714 static SUNXI_CCU_GATE_HWS(bus_uart6_clk, "bus-uart6", apb1_hws, 0x90c,
715 BIT(6), 0);
716 static SUNXI_CCU_GATE_HWS(bus_uart7_clk, "bus-uart7", apb1_hws, 0x90c,
717 BIT(7), 0);
719 static SUNXI_CCU_GATE_HWS(bus_i2c0_clk, "bus-i2c0", apb1_hws, 0x91c, BIT(0), 0);
720 static SUNXI_CCU_GATE_HWS(bus_i2c1_clk, "bus-i2c1", apb1_hws, 0x91c, BIT(1), 0);
721 static SUNXI_CCU_GATE_HWS(bus_i2c2_clk, "bus-i2c2", apb1_hws, 0x91c, BIT(2), 0);
722 static SUNXI_CCU_GATE_HWS(bus_i2c3_clk, "bus-i2c3", apb1_hws, 0x91c, BIT(3), 0);
723 static SUNXI_CCU_GATE_HWS(bus_i2c4_clk, "bus-i2c4", apb1_hws, 0x91c, BIT(4), 0);
724 static SUNXI_CCU_GATE_HWS(bus_i2c5_clk, "bus-i2c5", apb1_hws, 0x91c, BIT(5), 0);
726 static SUNXI_CCU_GATE_HWS(bus_can_clk, "bus-can", apb1_hws, 0x92c, BIT(0), 0);
738 24, 3, /* mux */
739 BIT(31), /* gate */
744 24, 3, /* mux */
745 BIT(31), /* gate */
750 24, 3, /* mux */
751 BIT(31), /* gate */
756 24, 3, /* mux */
757 BIT(31), /* gate */
759 static SUNXI_CCU_GATE_HWS(bus_spi0_clk, "bus-spi0", ahb_hws, 0x96c, BIT(0), 0);
760 static SUNXI_CCU_GATE_HWS(bus_spi1_clk, "bus-spi1", ahb_hws, 0x96c, BIT(1), 0);
761 static SUNXI_CCU_GATE_HWS(bus_spi2_clk, "bus-spi2", ahb_hws, 0x96c, BIT(2), 0);
762 static SUNXI_CCU_GATE_HWS(bus_spifc_clk, "bus-spifc", ahb_hws, 0x96c,
763 BIT(3), 0);
765 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(emac0_25M_clk, "emac0-25M",
767 0x970, BIT(31) | BIT(30), 6, 0);
768 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(emac1_25M_clk, "emac1-25M",
770 0x974, BIT(31) | BIT(30), 6, 0);
771 static SUNXI_CCU_GATE_HWS(bus_emac0_clk, "bus-emac0", ahb_hws, 0x97c,
772 BIT(0), 0);
773 static SUNXI_CCU_GATE_HWS(bus_emac1_clk, "bus-emac1", ahb_hws, 0x98c,
774 BIT(0), 0);
781 static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ir_rx_clk, "ir-rx", ir_rx_parents, 0x990,
783 24, 1, /* mux */
784 BIT(31), /* gate */
786 static SUNXI_CCU_GATE_HWS(bus_ir_rx_clk, "bus-ir-rx", apb0_hws, 0x99c,
787 BIT(0), 0);
793 static SUNXI_CCU_M_DATA_WITH_MUX_GATE(ir_tx_clk, "ir-tx", ir_tx_ledc_parents,
796 24, 1, /* mux */
797 BIT(31), /* gate */
799 static SUNXI_CCU_GATE_HWS(bus_ir_tx_clk, "bus-ir-tx", apb0_hws, 0x9cc,
800 BIT(0), 0);
804 BIT(31), /* gate */
808 BIT(31), /* gate */
810 static SUNXI_CCU_GATE_HWS(bus_gpadc0_clk, "bus-gpadc0", ahb_hws, 0x9ec,
811 BIT(0), 0);
812 static SUNXI_CCU_GATE_HWS(bus_gpadc1_clk, "bus-gpadc1", ahb_hws, 0x9ec,
813 BIT(1), 0);
815 static SUNXI_CCU_GATE_HWS(bus_ths_clk, "bus-ths", apb0_hws, 0x9fc, BIT(0), 0);
819 * a 2x multiplier from osc24M synchronized by pll-periph0, and is also used by
834 .enable = BIT(31),
836 .shift = 24,
844 .hw.init = CLK_HW_INIT_PARENTS_DATA("usb-ohci0",
852 .enable = BIT(31),
854 .shift = 24,
862 .hw.init = CLK_HW_INIT_PARENTS_DATA("usb-ohci1",
869 static SUNXI_CCU_GATE_HWS(bus_ohci0_clk, "bus-ohci0", ahb_hws, 0xa8c,
870 BIT(0), 0);
871 static SUNXI_CCU_GATE_HWS(bus_ohci1_clk, "bus-ohci1", ahb_hws, 0xa8c,
872 BIT(1), 0);
873 static SUNXI_CCU_GATE_HWS(bus_ehci0_clk, "bus-ehci0", ahb_hws, 0xa8c,
874 BIT(4), 0);
875 static SUNXI_CCU_GATE_HWS(bus_ehci1_clk, "bus-ehci1", ahb_hws, 0xa8c,
876 BIT(5), 0);
877 static SUNXI_CCU_GATE_HWS(bus_otg_clk, "bus-otg", ahb_hws, 0xa8c, BIT(8), 0);
879 static SUNXI_CCU_GATE_HWS(bus_lradc_clk, "bus-lradc", apb0_hws, 0xa9c,
880 BIT(0), 0);
887 static SUNXI_CCU_M_DATA_WITH_MUX_GATE(pcie_aux_clk, "pcie-aux",
890 24, 1, /* mux */
891 BIT(31), /* gate */
894 static SUNXI_CCU_GATE_HWS(bus_display0_top_clk, "bus-display0-top", ahb_hws,
895 0xabc, BIT(0), 0);
896 static SUNXI_CCU_GATE_HWS(bus_display1_top_clk, "bus-display1-top", ahb_hws,
897 0xacc, BIT(0), 0);
899 static SUNXI_CCU_GATE_DATA(hdmi_24M_clk, "hdmi-24M", osc24M, 0xb04, BIT(31), 0);
901 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(hdmi_cec_32k_clk, "hdmi-cec-32k",
903 0xb10, BIT(30), 36621, 0);
909 static SUNXI_CCU_MUX_DATA_WITH_GATE(hdmi_cec_clk, "hdmi-cec", hdmi_cec_parents,
911 24, 1, /* mux */
912 BIT(31), /* gate */
915 static SUNXI_CCU_GATE_HWS(bus_hdmi_clk, "bus-hdmi", ahb_hws, 0xb1c, BIT(0), 0);
922 static SUNXI_CCU_M_DATA_WITH_MUX_GATE(mipi_dsi0_clk, "mipi-dsi0",
925 24, 3, /* mux */
926 BIT(31), /* gate */
929 static SUNXI_CCU_M_DATA_WITH_MUX_GATE(mipi_dsi1_clk, "mipi-dsi1",
932 24, 3, /* mux */
933 BIT(31), /* gate */
936 static SUNXI_CCU_GATE_HWS(bus_mipi_dsi0_clk, "bus-mipi-dsi0", ahb_hws, 0xb4c,
937 BIT(0), 0);
939 static SUNXI_CCU_GATE_HWS(bus_mipi_dsi1_clk, "bus-mipi-dsi1", ahb_hws, 0xb4c,
940 BIT(1), 0);
951 static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_parents,
954 24, 3, /* mux */
955 BIT(31), /* gate */
958 static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd1_clk, "tcon-lcd1", tcon_parents,
961 24, 3, /* mux */
962 BIT(31), /* gate */
972 static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_lcd2_clk, "tcon-lcd2",
975 24, 3, /* mux */
976 BIT(31), /* gate */
979 static SUNXI_CCU_M_HW_WITH_MUX_GATE(combophy_dsi0_clk, "combophy-dsi0",
982 24, 3, /* mux */
983 BIT(31), /* gate */
986 static SUNXI_CCU_M_HW_WITH_MUX_GATE(combophy_dsi1_clk, "combophy-dsi1",
989 24, 3, /* mux */
990 BIT(31), /* gate */
993 static SUNXI_CCU_GATE_HWS(bus_tcon_lcd0_clk, "bus-tcon-lcd0", ahb_hws, 0xb7c,
994 BIT(0), 0);
995 static SUNXI_CCU_GATE_HWS(bus_tcon_lcd1_clk, "bus-tcon-lcd1", ahb_hws, 0xb7c,
996 BIT(1), 0);
997 static SUNXI_CCU_GATE_HWS(bus_tcon_lcd2_clk, "bus-tcon-lcd2", ahb_hws, 0xb7c,
998 BIT(2), 0);
1000 static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0", tcon_tv_parents,
1003 24, 3, /* mux */
1004 BIT(31), /* gate */
1007 static SUNXI_CCU_M_HW_WITH_MUX_GATE(tcon_tv1_clk, "tcon-tv1", tcon_tv_parents,
1010 24, 3, /* mux */
1011 BIT(31), /* gate */
1014 static SUNXI_CCU_GATE_HWS(bus_tcon_tv0_clk, "bus-tcon-tv0", ahb_hws, 0xb9c,
1015 BIT(0), 0);
1016 static SUNXI_CCU_GATE_HWS(bus_tcon_tv1_clk, "bus-tcon-tv1", ahb_hws, 0xb9c,
1017 BIT(1), 0);
1028 24, 3, /* mux */
1029 BIT(31), /* gate */
1032 static SUNXI_CCU_GATE_HWS(bus_edp_clk, "bus-edp", ahb_hws, 0xbbc, BIT(0), 0);
1037 24, 1, /* mux */
1038 BIT(31), /* gate */
1041 static SUNXI_CCU_GATE_HWS(bus_ledc_clk, "bus-ledc", apb0_hws, 0xbfc, BIT(0), 0);
1050 static SUNXI_CCU_M_HW_WITH_MUX_GATE(csi_top_clk, "csi-top", csi_top_parents,
1053 24, 3, /* mux */
1054 BIT(31), /* gate */
1064 static SUNXI_CCU_DUALDIV_MUX_GATE(csi_mclk0_clk, "csi-mclk0", csi_mclk_parents,
1068 24, 3, /* mux */
1069 BIT(31), /* gate */
1072 static SUNXI_CCU_DUALDIV_MUX_GATE(csi_mclk1_clk, "csi-mclk1", csi_mclk_parents,
1076 24, 3, /* mux */
1077 BIT(31), /* gate */
1080 static SUNXI_CCU_DUALDIV_MUX_GATE(csi_mclk2_clk, "csi-mclk2", csi_mclk_parents,
1084 24, 3, /* mux */
1085 BIT(31), /* gate */
1088 static SUNXI_CCU_DUALDIV_MUX_GATE(csi_mclk3_clk, "csi-mclk3", csi_mclk_parents,
1092 24, 3, /* mux */
1093 BIT(31), /* gate */
1096 static SUNXI_CCU_GATE_HWS(bus_csi_clk, "bus-csi", ahb_hws, 0xc1c, BIT(0), 0);
1106 24, 3, /* mux */
1107 BIT(31), /* gate */
1119 24, 3, /* mux */
1120 BIT(31), /* gate */
1123 static SUNXI_CCU_GATE_DATA(fanout_24M_clk, "fanout-24M", osc24M,
1124 0xf30, BIT(0), 0);
1125 static SUNXI_CCU_GATE_DATA_WITH_PREDIV(fanout_12M_clk, "fanout-12M", osc24M,
1126 0xf30, BIT(1), 2, 0);
1127 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_16M_clk, "fanout-16M",
1129 0xf30, BIT(2), 30, 0);
1130 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_25M_clk, "fanout-25M",
1132 0xf30, BIT(3), 48, 0);
1133 static SUNXI_CCU_GATE_HWS_WITH_PREDIV(fanout_50M_clk, "fanout-50M",
1135 0xf30, BIT(4), 24, 0);
1143 static SUNXI_CCU_DUALDIV_MUX_GATE(fanout_27M_clk, "fanout-27M",
1147 24, 2, /* mux */
1148 BIT(31), /* gate */
1154 static SUNXI_CCU_DUALDIV_MUX_GATE(fanout_pclk_clk, "fanout-pclk",
1160 BIT(31), /* gate */
1164 { .fw_name = "losc-fanout" },
1176 BIT(21), /* gate */
1181 BIT(22), /* gate */
1186 BIT(23), /* gate */
1546 [RST_MBUS] = { 0x540, BIT(30) },
1547 [RST_BUS_NSI] = { 0x54c, BIT(16) },
1548 [RST_BUS_DE] = { 0x60c, BIT(16) },
1549 [RST_BUS_DI] = { 0x62c, BIT(16) },
1550 [RST_BUS_G2D] = { 0x63c, BIT(16) },
1551 [RST_BUS_SYS] = { 0x64c, BIT(16) },
1552 [RST_BUS_GPU] = { 0x67c, BIT(16) },
1553 [RST_BUS_CE] = { 0x68c, BIT(16) },
1554 [RST_BUS_SYS_CE] = { 0x68c, BIT(17) },
1555 [RST_BUS_VE] = { 0x69c, BIT(16) },
1556 [RST_BUS_DMA] = { 0x70c, BIT(16) },
1557 [RST_BUS_MSGBOX] = { 0x71c, BIT(16) },
1558 [RST_BUS_SPINLOCK] = { 0x72c, BIT(16) },
1559 [RST_BUS_CPUXTIMER] = { 0x74c, BIT(16) },
1560 [RST_BUS_DBG] = { 0x78c, BIT(16) },
1561 [RST_BUS_PWM0] = { 0x7ac, BIT(16) },
1562 [RST_BUS_PWM1] = { 0x7ac, BIT(17) },
1563 [RST_BUS_DRAM] = { 0x80c, BIT(16) },
1564 [RST_BUS_NAND] = { 0x82c, BIT(16) },
1565 [RST_BUS_MMC0] = { 0x84c, BIT(16) },
1566 [RST_BUS_MMC1] = { 0x84c, BIT(17) },
1567 [RST_BUS_MMC2] = { 0x84c, BIT(18) },
1568 [RST_BUS_SYSDAP] = { 0x88c, BIT(16) },
1569 [RST_BUS_UART0] = { 0x90c, BIT(16) },
1570 [RST_BUS_UART1] = { 0x90c, BIT(17) },
1571 [RST_BUS_UART2] = { 0x90c, BIT(18) },
1572 [RST_BUS_UART3] = { 0x90c, BIT(19) },
1573 [RST_BUS_UART4] = { 0x90c, BIT(20) },
1574 [RST_BUS_UART5] = { 0x90c, BIT(21) },
1575 [RST_BUS_UART6] = { 0x90c, BIT(22) },
1576 [RST_BUS_UART7] = { 0x90c, BIT(23) },
1577 [RST_BUS_I2C0] = { 0x91c, BIT(16) },
1578 [RST_BUS_I2C1] = { 0x91c, BIT(17) },
1579 [RST_BUS_I2C2] = { 0x91c, BIT(18) },
1580 [RST_BUS_I2C3] = { 0x91c, BIT(19) },
1581 [RST_BUS_I2C4] = { 0x91c, BIT(20) },
1582 [RST_BUS_I2C5] = { 0x91c, BIT(21) },
1583 [RST_BUS_CAN] = { 0x92c, BIT(16) },
1584 [RST_BUS_SPI0] = { 0x96c, BIT(16) },
1585 [RST_BUS_SPI1] = { 0x96c, BIT(17) },
1586 [RST_BUS_SPI2] = { 0x96c, BIT(18) },
1587 [RST_BUS_SPIFC] = { 0x96c, BIT(19) },
1588 [RST_BUS_EMAC0] = { 0x97c, BIT(16) },
1589 [RST_BUS_EMAC1] = { 0x98c, BIT(16) | BIT(17) }, /* GMAC1-AXI */
1590 [RST_BUS_IR_RX] = { 0x99c, BIT(16) },
1591 [RST_BUS_IR_TX] = { 0x9cc, BIT(16) },
1592 [RST_BUS_GPADC0] = { 0x9ec, BIT(16) },
1593 [RST_BUS_GPADC1] = { 0x9ec, BIT(17) },
1594 [RST_BUS_THS] = { 0x9fc, BIT(16) },
1595 [RST_USB_PHY0] = { 0xa70, BIT(30) },
1596 [RST_USB_PHY1] = { 0xa74, BIT(30) },
1597 [RST_BUS_OHCI0] = { 0xa8c, BIT(16) },
1598 [RST_BUS_OHCI1] = { 0xa8c, BIT(17) },
1599 [RST_BUS_EHCI0] = { 0xa8c, BIT(20) },
1600 [RST_BUS_EHCI1] = { 0xa8c, BIT(21) },
1601 [RST_BUS_OTG] = { 0xa8c, BIT(24) },
1602 [RST_BUS_3] = { 0xa8c, BIT(25) }, /* BSP + register */
1603 [RST_BUS_LRADC] = { 0xa9c, BIT(16) },
1604 [RST_BUS_PCIE_USB3] = { 0xaac, BIT(16) },
1605 [RST_BUS_DISPLAY0_TOP] = { 0xabc, BIT(16) },
1606 [RST_BUS_DISPLAY1_TOP] = { 0xacc, BIT(16) },
1607 [RST_BUS_HDMI_MAIN] = { 0xb1c, BIT(16) },
1608 [RST_BUS_HDMI_SUB] = { 0xb1c, BIT(17) },
1609 [RST_BUS_MIPI_DSI0] = { 0xb4c, BIT(16) },
1610 [RST_BUS_MIPI_DSI1] = { 0xb4c, BIT(17) },
1611 [RST_BUS_TCON_LCD0] = { 0xb7c, BIT(16) },
1612 [RST_BUS_TCON_LCD1] = { 0xb7c, BIT(17) },
1613 [RST_BUS_TCON_LCD2] = { 0xb7c, BIT(18) },
1614 [RST_BUS_TCON_TV0] = { 0xb9c, BIT(16) },
1615 [RST_BUS_TCON_TV1] = { 0xb9c, BIT(17) },
1616 [RST_BUS_LVDS0] = { 0xbac, BIT(16) },
1617 [RST_BUS_LVDS1] = { 0xbac, BIT(17) },
1618 [RST_BUS_EDP] = { 0xbbc, BIT(16) },
1619 [RST_BUS_VIDEO_OUT0] = { 0xbcc, BIT(16) },
1620 [RST_BUS_VIDEO_OUT1] = { 0xbcc, BIT(17) },
1621 [RST_BUS_LEDC] = { 0xbfc, BIT(16) },
1622 [RST_BUS_CSI] = { 0xc1c, BIT(16) },
1623 [RST_BUS_ISP] = { 0xc2c, BIT(16) }, /* BSP + register */
1662 * not support a separate enable and gate bit. We present the in sun55i_a523_ccu_probe()
1663 * gate bit(27) as the enable bit, but then have to set the in sun55i_a523_ccu_probe()
1668 val |= BIT(31) | BIT(30) | BIT(29); in sun55i_a523_ccu_probe()
1674 val &= ~(BIT(1) | BIT(0)); in sun55i_a523_ccu_probe()
1677 ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun55i_a523_ccu_desc); in sun55i_a523_ccu_probe()
1685 { .compatible = "allwinner,sun55i-a523-ccu" },
1692 .name = "sun55i-a523-ccu",