Lines Matching +full:5 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2025 Chen-Yu Tsai <wens@csie.org>
6 * Copyright (C) 2023-2024 Arm Ltd.
9 #include <linux/clk-provider.h>
14 #include <dt-bindings/clock/sun55i-a523-mcu-ccu.h>
15 #include <dt-bindings/reset/sun55i-a523-mcu-ccu.h>
31 { .fw_name = "r-ahb" }
35 { .fw_name = "r-apb0" }
40 { .rate = 2167603200, .pattern = 0xa000a234, .m = 1, .n = 90 }, /* div2->22.5792 */
41 { .rate = 2359296000, .pattern = 0xa0009ba6, .m = 1, .n = 98 }, /* div2->24.576 */
42 { .rate = 1806336000, .pattern = 0xa000872b, .m = 1, .n = 75 }, /* div5->22.576 */
46 .enable = BIT(27),
47 .lock = BIT(28),
50 .sdm = _SUNXI_CCU_SDM(pll_audio1_sdm_table, BIT(24),
51 0x010, BIT(31)),
57 .hw.init = CLK_HW_INIT_PARENTS_DATA("pll-audio1",
64 * /2 and /5 dividers are actually programmable, but we just use the
69 static CLK_FIXED_FACTOR_HWS(pll_audio1_div2_clk, "pll-audio1-div2",
72 static CLK_FIXED_FACTOR_HWS(pll_audio1_div5_clk, "pll-audio1-div5",
73 pll_audio1_div_parents, 5, 1,
76 static SUNXI_CCU_M_WITH_GATE(audio_out_clk, "audio-out",
77 "pll-audio1-div2", 0x01c,
78 0, 5, BIT(31), CLK_SET_RATE_PARENT);
93 static SUNXI_CCU_M_DATA_WITH_MUX_GATE(dsp_clk, "mcu-dsp", dsp_parents, 0x0020,
94 0, 5, /* M */
96 BIT(31), /* gate */
100 { .fw_name = "pll-audio0-4x" },
106 0, 5, /* M */
107 5, 5, /* P */
109 BIT(31), /* gate */
112 0, 5, /* M */
113 5, 5, /* P */
115 BIT(31), /* gate */
118 0, 5, /* M */
119 5, 5, /* P */
121 BIT(31), /* gate */
124 0, 5, /* M */
125 5, 5, /* P */
127 BIT(31), /* gate */
131 { .fw_name = "pll-periph0-300m" },
135 static SUNXI_CCU_DUALDIV_MUX_GATE(i2s3_asrc_clk, "i2s3-asrc",
137 0, 5, /* M */
138 5, 5, /* P */
140 BIT(31), /* gate */
143 static SUNXI_CCU_GATE_DATA(bus_i2s0_clk, "bus-i2s0", apb, 0x040, BIT(0), 0);
144 static SUNXI_CCU_GATE_DATA(bus_i2s1_clk, "bus-i2s1", apb, 0x040, BIT(1), 0);
145 static SUNXI_CCU_GATE_DATA(bus_i2s2_clk, "bus-i2s2", apb, 0x040, BIT(2), 0);
146 static SUNXI_CCU_GATE_DATA(bus_i2s3_clk, "bus-i2s3", apb, 0x040, BIT(3), 0);
149 { .fw_name = "pll-audio0-4x" },
153 static SUNXI_CCU_DUALDIV_MUX_GATE(spdif_tx_clk, "spdif-tx",
155 0, 5, /* M */
156 5, 5, /* P */
158 BIT(31), /* gate */
160 static SUNXI_CCU_DUALDIV_MUX_GATE(spdif_rx_clk, "spdif-rx",
162 0, 5, /* M */
163 5, 5, /* P */
165 BIT(31), /* gate */
168 static SUNXI_CCU_GATE_DATA(bus_spdif_clk, "bus-spdif", apb, 0x04c, BIT(0), 0);
171 0, 5, /* M */
172 5, 5, /* P */
174 BIT(31), /* gate */
177 static SUNXI_CCU_GATE_DATA(bus_dmic_clk, "bus-dmic", apb, 0x054, BIT(0), 0);
179 static SUNXI_CCU_DUALDIV_MUX_GATE(audio_dac_clk, "audio-dac",
181 0, 5, /* M */
182 5, 5, /* P */
184 BIT(31), /* gate */
186 static SUNXI_CCU_DUALDIV_MUX_GATE(audio_adc_clk, "audio-adc",
188 0, 5, /* M */
189 5, 5, /* P */
191 BIT(31), /* gate */
194 static SUNXI_CCU_GATE_DATA(bus_audio_codec_clk, "bus-audio-codec",
195 apb, 0x060, BIT(0), 0);
197 static SUNXI_CCU_GATE_DATA(bus_dsp_msgbox_clk, "bus-dsp-msgbox",
198 ahb, 0x068, BIT(0), 0);
199 static SUNXI_CCU_GATE_DATA(bus_dsp_cfg_clk, "bus-dsp-cfg",
200 apb, 0x06c, BIT(0), 0);
202 static SUNXI_CCU_GATE_DATA(bus_npu_hclk, "bus-npu-hclk", ahb, 0x070, BIT(1), 0);
203 static SUNXI_CCU_GATE_DATA(bus_npu_aclk, "bus-npu-aclk", ahb, 0x070, BIT(2), 0);
209 { .fw_name = "r-ahb" }
211 static SUNXI_CCU_P_DATA_WITH_MUX_GATE(mcu_timer0_clk, "mcu-timer0", timer_parents,
215 BIT(0), /* gate */
217 static SUNXI_CCU_P_DATA_WITH_MUX_GATE(mcu_timer1_clk, "mcu-timer1", timer_parents,
221 BIT(0), /* gate */
223 static SUNXI_CCU_P_DATA_WITH_MUX_GATE(mcu_timer2_clk, "mcu-timer2", timer_parents,
227 BIT(0), /* gate */
229 static SUNXI_CCU_P_DATA_WITH_MUX_GATE(mcu_timer3_clk, "mcu-timer3", timer_parents,
233 BIT(0), /* gate */
235 static SUNXI_CCU_P_DATA_WITH_MUX_GATE(mcu_timer4_clk, "mcu-timer4", timer_parents,
239 BIT(0), /* gate */
241 static SUNXI_CCU_P_DATA_WITH_MUX_GATE(mcu_timer5_clk, "mcu-timer5", timer_parents,
245 BIT(0), /* gate */
247 static SUNXI_CCU_GATE_DATA(bus_mcu_timer_clk, "bus-mcu-timer", ahb, 0x08c, BIT(0), 0);
248 static SUNXI_CCU_GATE_DATA(bus_mcu_dma_clk, "bus-mcu-dma", ahb, 0x104, BIT(0), 0);
250 static SUNXI_CCU_GATE_DATA(tzma0_clk, "tzma0", ahb, 0x108, BIT(0), 0);
251 static SUNXI_CCU_GATE_DATA(tzma1_clk, "tzma1", ahb, 0x10c, BIT(0), 0);
253 static SUNXI_CCU_GATE_DATA(bus_pubsram_clk, "bus-pubsram", ahb, 0x114, BIT(0), 0);
260 static SUNXI_CCU_GATE_FW(mbus_mcu_clk, "mbus-mcu", "mbus", 0x11c, BIT(1), 0);
261 static SUNXI_CCU_GATE_HW(mbus_mcu_dma_clk, "mbus-mcu-dma",
262 &mbus_mcu_clk.common.hw, 0x11c, BIT(0), 0);
272 27, 3, BIT(31), 0);
274 static SUNXI_CCU_GATE_DATA(bus_riscv_cfg_clk, "bus-riscv-cfg", ahb,
275 0x124, BIT(0), 0);
276 static SUNXI_CCU_GATE_DATA(bus_riscv_msgbox_clk, "bus-riscv-msgbox", ahb,
277 0x128, BIT(0), 0);
279 static SUNXI_CCU_MUX_DATA_WITH_GATE(mcu_pwm0_clk, "mcu-pwm0",
281 24, 3, BIT(31), 0);
282 static SUNXI_CCU_GATE_DATA(bus_mcu_pwm0_clk, "bus-mcu-pwm0", apb,
283 0x134, BIT(0), 0);
386 [RST_BUS_MCU_I2S0] = { 0x0040, BIT(16) },
387 [RST_BUS_MCU_I2S1] = { 0x0040, BIT(17) },
388 [RST_BUS_MCU_I2S2] = { 0x0040, BIT(18) },
389 [RST_BUS_MCU_I2S3] = { 0x0040, BIT(19) },
390 [RST_BUS_MCU_SPDIF] = { 0x004c, BIT(16) },
391 [RST_BUS_MCU_DMIC] = { 0x0054, BIT(16) },
392 [RST_BUS_MCU_AUDIO_CODEC] = { 0x0060, BIT(16) },
393 [RST_BUS_MCU_DSP_MSGBOX] = { 0x0068, BIT(16) },
394 [RST_BUS_MCU_DSP_CFG] = { 0x006c, BIT(16) },
395 [RST_BUS_MCU_NPU] = { 0x0070, BIT(16) },
396 [RST_BUS_MCU_TIMER] = { 0x008c, BIT(16) },
398 [RST_BUS_MCU_DSP_DEBUG] = { 0x0100, BIT(16) },
399 [RST_BUS_MCU_DSP] = { 0x0100, BIT(17) },
400 [RST_BUS_MCU_DMA] = { 0x0104, BIT(16) },
401 [RST_BUS_MCU_PUBSRAM] = { 0x0114, BIT(16) },
402 [RST_BUS_MCU_RISCV_CFG] = { 0x0124, BIT(16) },
403 [RST_BUS_MCU_RISCV_DEBUG] = { 0x0124, BIT(17) },
404 [RST_BUS_MCU_RISCV_CORE] = { 0x0124, BIT(18) },
405 [RST_BUS_MCU_RISCV_MSGBOX] = { 0x0128, BIT(16) },
406 [RST_BUS_MCU_PWM0] = { 0x0134, BIT(16) },
433 * not support a separate enable and gate bit. We present the in sun55i_a523_mcu_ccu_probe()
434 * gate bit(27) as the enable bit, but then have to set the in sun55i_a523_mcu_ccu_probe()
437 val |= BIT(31) | BIT(30) | BIT(29); in sun55i_a523_mcu_ccu_probe()
439 /* Enforce p1 = 5, p0 = 2 (the default) for PLL_AUDIO1 */ in sun55i_a523_mcu_ccu_probe()
445 ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun55i_a523_mcu_ccu_desc); in sun55i_a523_mcu_ccu_probe()
453 { .compatible = "allwinner,sun55i-a523-mcu-ccu" },
460 .name = "sun55i-a523-mcu-ccu",